82C85 Datasheet, PDF (19/21 Pages) Intersil Corporation – CMOS Static Clock Controller/Generator

Test Load Circuits
PASSIVE LOAD
V
FROM OUTPUT
UNDER TEST
R
CL
SEE NOTE 3
82C85
DYNAMIC LOAD
V
FROM OUTPUT
UNDER TEST
R
CL
SEE NOTE 3
R = 360 at V = 2.25 for CLK and CLK50 outputs
R = 470 at V = 2.87 for all other outputs (Except X2)
NOTES:
1. C_L = 100pF for CLK and CLK50 output
2. C_L = 50pF minimum for all other outputs
3. C_L = Includes probe and jig capacitance
TCHCL, TCLCH LOAD CIRCUIT (USING X1, X2)
C1
C2
X1
CLK
X2
F/C
CLK50
CSYNC
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 1)
I_OL = 5mA, IOH = -5mA for CLK and CLK50 outputs
I_OL = 5mA, IOH = -2.5mA for all other outputs (Except X2)
I_OL = 2.5mA, IOH = -1.0mA for X2 output (DC Performance
characteristic only)
V_TRIP = 1.4V
TCHCL, TCLCH LOAD CIRCUIT (USING EFI)
PULSE
GENERATOR
V_CC
EF1
CLK
F/C
CLK50
CSYNC
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 1)
TRYLCL, TRYHCH LOAD CIRCUIT (USING X1, X2)
V_CC
C1
24MHZ
C2
PULSE
GENERATOR
TRIGGER
AEN1
X1
CLK
READY
X2
RDY2
F/C
AEN2
CSYNC
OSC
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 2)
TRYLCL, TRYHCH LOAD CIRCUIT (USING EFI)
PULSE
GENERATOR
TRIGGER
PULSE
GENERATOR
V_CC
EF1
CLK
F/C
AEN1
RDY2 ^READY
AEN2
CSYNC
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 2)
A.C. Testing Input, Output Waveform
INPUT
V_IH + 0.4V
1.5V
V_IL + 0.4V
315
OUTPUT
V_OH
1.5V
V_OL