82C85 Datasheet, PDF (17/21 Pages) Intersil Corporation – CMOS Static Clock Controller/Generator

Timing Waveforms (Continued)
82C85
EFI
OR
OSC
PCLK
SLO/FST
CLK
CLK50
FIGURE 15. SLO/FST TIMING OVERVIEW
NOTE: See Fast to Slow Clock Mode Transition for Detailed Timing; See Slow to Fast Clock Mode Transition for Detailed Timing
EFI
OR
OSC
PCLK
TSFPC
(22)
(SEE NOTE)
SLO/FST
197 TO 200 EFI
OR OSC CYCLES
TSFPC
(22)
(SEE NOTE)
CLK
CLK50
FIGURE 16. FAST TO SLOW CLOCK MODE TRANSITION
NOTE: IF TSFPC is not met on one edge of PLCK. SLO/FST will be recognized on the next edge of PLCK.
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