82C85 Datasheet, PDF (16/21 Pages) Intersil Corporation – CMOS Static Clock Controller/Generator

Timing Waveforms (Continued)
82C85
RES
CLK
RESET
(21) TSHSL
(17)
TI1HCL
(17)
TI1HCL
(36)
TCLIL
(36)
TCLIL
(42)
TRST
FIGURE 13. RESET TIMING (CLK RUNNING WITH F/C LOW-OSC MODE)
(CLK RUNNING-OR STOPPED WITH F/C HIGH EFI MODE)
RES
CLK
(21) TSHSL
(36)
TCLIL
RESET
OSCILLATOR
STARTUP
TIME
X1
8192
CYCLES
(39)
TOST
(42)
TRST
FIGURE 14. RESET TIMING (OSCILLATOR STOPPED, F/C LOW)
NOTE: CLK, CLK50, PCLK Remain in the High State until RES goes high and 8192 valid oscillator cycles have been registered by the 82C85
internal counter (TOST time period). After RES goes high and CLK, CLK50, PCLK become active, the RESET output will remain high
for minimum of 16 CLK cycles (TRST).
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