82C85 Datasheet, PDF (12/21 Pages) Intersil Corporation – CMOS Static Clock Controller/Generator

82C85
AC Electrical Specifications
V_CC = 5V ±10%;T_A = 0^oC to +70^oC (C82C85);
T_A = -40^oC to +85^oC (I82C85);
T_A = -55^oC to +125^oC (M82C85)
LIMITS
(Continued)
SYMBOL
PARAMETER
MIN
MAX
UNITS
CONDITIONS
(27) TCLCH
CLK LOW Time
(2/3 TCLCL)-15
-
ns
(28) T5CHCL
CLK50 HIGH Time
(1/2 TCLCL)-7.5
-
ns
(29) T5CLCH
CLK50 LOW Time
(1/2 TCLCL)-7.5
-
ns
(30) TCH1CH2 CLK/CLK50 Rise Time
-
8
ns
1.0V to 3.5V
(31) TCL2CL1 CLK/CLK50 Fall Time
-
8
ns
1.0V to 3.5V
(32) TPHPL
PCLK HIGH Time
TCLCL-20
-
ns
(33) TPLPH
PCLK LOW Time
TCLCL-20
-
ns
(34) TRYLCL
Ready Inactive to CLK
-8
-
ns
Note 4
(35) TRYHCH
Ready Active to CLK
2/3(TCLCL)-15
-
ns
Note 3
(36) TCLIL
CLK to Reset Delay
-
40
ns
(37) TCLPH
CLK to PCLK HIGH Delay
-
22
ns
(38) TCLPL
CLK to PCLK LOW Delay
-
22
ns
(39) TOST
Start/Reset Valid to Clock LOW
-
2
ms
Typ. - Note 8
(40) TOLOH
Output Rise Time (except CLK)
-
15
ns
From 0.8V to 2.0V
(41) TOHOL
Output Fall Time (except CLK)
-
12
ns
From 2.0V to 0.8V
(42) TRST
RESET output HIGH Time
16 x TCLCL
-
ns
(43) TCLC50L CLK LOW to CLK50 LOW Skew
-
5
ns
NOTES:
1. Slow and Fast Modes.
2. Setup and hold necessary only to guarantee recognition at next clock.
3. Applies only to T3, TW states.
4. Applies only to T2 states.
5. All timing delays are measured at 1.5V unless otherwise noted.
6. Input signals must switch between V_IL max - 0.4 and V_IH min + 0.4 volts
7. Timing measurements made with EFI duty cycle = 50%.
8. Oscillator start up time depends on several factors including crystal frequency, crystal manufacturer, capacitive load, temperature, power
supply voltage, etc. This parameter is given for information only.
9. Output signals switch between V_OH and V_OL unless otherwise specified.
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