82C85 Datasheet, PDF (2/21 Pages) Intersil Corporation – CMOS Static Clock Controller/Generator

82C85
Pin Descriptions
SYMBOL
X1
X2
DIP PIN
NUMBER
23
22
TYPE
I
O
EFI
20
I
F/C
19
I
START
11
I
SO
13
I
S1
14
I
S2/STOP
15
I
SLO/FST
12
I
CLK
8
O
CLK50
10
O
PCLK
2
O
OSC
18
O
DESCRIPTION
CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystal frequency
must be 3 times the maximum desired processor clock frequency. X1 is the oscillator circuit input
and X2 is the output of the oscillator circuit. If the crystal inputs are not used, X1 must be tied to V_CC
or GND, and X2 should be left open.
EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input signal. This
input signal should be a square wave with a frequency of three times the maximum desired CLK
output frequency. If the crystal inputs are not used. XI must be tied to V_CC or GND, and X2 should
be left open.
FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI input as the
main frequency source. When F/C is LOW, the 82C85 clocks are derived from the crystal oscillator
circuit. When F/C is HIGH, CLK is generated from the EFI input. F/C cannot be dynamically
switched during normal operation.
A low-to-high transition on START will restart the CLK, CLK50 and PCLK outputs after the appro-
priate restart sequence is completed.
When in the crystal mode (F/C LOW) with the oscillator stopped. The oscillator will be restarted
when a Start command is received. The CLK, CLK50 and PCLK outputs will start after the oscillator
input signal (X1) reaches the Schmitt trigger input threshold and 8K internal counter reaches termi-
nal count. If F/C is HIGH (EFI mode), CLK, CLK50 and PCLK will restart within 3 EFI cycles after
START is recognized.
The 82C85 will restart in the same mode (SLO/FST) in which it stopped. A high level on START
disables the STOP mode.
S2/STOP, S1, SO are used to stop the 82C85 clock outputs (CLK, CLK50, PCLK) and are sampled
by the rising edge of CLK, CLK50 and PCLK are stopped by S2/STOP, S1, SO being in the LHH
state on the low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring
on the previous low-to-high CLK transition. CLK and CLK50 stop in the high state when F/C is low
and may stop in either the high or low state when F/C is high. PCLK stops in its current state (high
or low).
When in the crystal mode (F/C) low and a STOP command is issued, the 82C85 oscillator will stop along
with the CLK, CLK50 and PCLK outputs. When in the EFI mode, only the CLK, CLK50 and PCLK out-
puts will be halted. The oscillator circuit if operational, will continue to run. The oscillator and/or clock is
restarted by the START input signal going true (HIGH) or the reset input (RES) going low.
SLO/FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the maximum
frequency (crystal or EFI frequency divided by 3). When LOW, CLK and CLK50 frequencies are
equal to the crystal or EFI frequency divided by 768. SLO/FST changes are internally synchronized
so proper CLK and CLK50 phase relationships are maintained and minimum pulse width specifica-
tions are met. START and STOP control of the oscillator or EFI is available in either the SLOW or
FAST frequency modes. The SLO/FST input must be held LOW for at least 195 OSC/EFI clock cy-
cles before it will be recognized. This eliminates unwanted frequency changes which could be
caused by glitches or noise transients. The SLO/FST input must be held HIGH for at least 6
OSC/EFI clock pulses to guarantee a transition to FAST mode operation.
PROCESSOR CLOCK: CLK is the clock output used by the 80C86 or 80C88 processor and other
peripheral devices. When SLO/FST is high, CLK has an output frequency which is equal to the crys-
tal or EFI input frequency divided by three. When SLO/FST is low, CLK has an output frequency
which is equal to the crystal or EFI input frequency divided by 768. CLK has a 33% duty cycle.
50% DUTY CYCLE CLOCK: CLK50 is an auxiliary clock with a 50% duty cycle and is synchronized
to the falling edge of CLK. When SLO/FST is high, CLK50 has an output frequency which is equal
to the crystal or EFI input frequency divided by 3. When SLO/FST is low, CLK50 has an output fre-
quency equal to the crystal or EFI input frequency divided by 768.
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is equal to the
crystal or EFI input frequency divided by 6 and has a 50% duty cycle. PCLK frequency is unaffected
by the state of the SLO/FST input.
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal
to that of the crystal oscillator circuit. OSC is unaffected by the state of the SLO/FST input.
When the 82C85 is in the crystal mode (F/C low) and a STOP command is issued, the OSC output
will stop in the HIGH state. When the 82C85 is in the EFI mode (F/C HIGH, the oscillator (if
operational) will continue to run when a STOP command is issued and OSC remains active.
298