82C85 Datasheet, PDF (11/21 Pages) Intersil Corporation – CMOS Static Clock Controller/Generator

82C85
AC Electrical Specifications
V_CC = 5V ±10%;T_A = 0^oC to +70^oC (C82C85);
T_A = -40^oC to +85^oC (I82C85);
T_A = -55^oC to +125^oC (M82C85)
LIMITS
SYMBOL
PARAMETER
MIN
MAX
TIMING REQUIREMENTS
(1) TEHEL
External Frequency HIGH Time
15
-
(2) TELEH
External Frequency LOW Time
15
-
(3) TELEL
EFI or Crystal Period
40
(4) TEFIDC
External Frequency Input Duty Cycle
45
(5) Fx
Crystal Frequency
2.4
(6) TR1VCL
RDY1, RDY2 Active Setup to CLK
35
(7) TR1VCH
RDY1, RDY2 Active Setup to CLK
35
(8) TR1VCL
RDY1, RDY2 Inactive Setup to CLK
35
(9) TCLR1X
RDY1, RDY2 Hold to CLK
0
(10) TAYVCL
ASYNC Setup to CLK
50
(11) TCLAYX
ASYNC Hold to CLK
0
(12) TA1VR1V AEN1, AEN2 Setup to RDY1, RDY2
15
(13) TCLA1X
AEN1, AEN2 Hold to CLK
0
(14) TYHEH
CSYNC Setup to EFI
10
(15) TEHYL
CSYNC Hold to EFI
10
(16) TYHYL
CSYNC Pulse Width
2TELEL
(17) TI1HCL
RES Setup to CLK
65
(18) TSVCH
S0, S1, S2/STOP Setup to CLK
35
(19) TCHSV
S0, S1, S2/STOP Hold to CLK
35
(20) TRSVCH
RES, START Setup to CLK
65
(21) TSHSL
RES (Low) or START (High) Pulse Width
TCLCLs3
(22) TSFPC
SLO/FST Setup to PCLK
TEHEL + 100
(23) TSTART
RES or START Valid to CLK Low
2TELEL + 2
(24) TSTOP
STOP Command Valid to CLK High
2TCHCH +
TRSVCH
TIMING RESPONSES
(25) TCLCL
CLK/CLK50 Cycle Period
125
(26) TCHCL
CLK HIGH Time
(1/3 TCLCL)+2
-
55
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3TCHCH
+ 34
-
-
UNITS
CONDITIONS
ns
ns
ns
%
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
90%-90% V_IN, Note 1,
f = 25MHz
10%-10% V_IN, Note 1,
f = 25MHz
Note 1
f = 25MHz, Note 1
Note 1
ASYNC = HIGH
ASYNC = LOW
Note 2
Note 2
Note 2
TCHCH = TCLCL
ns
Note 1
ns
307