X40030_06 Datasheet, PDF (6/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
PIN DESCRIPTION (Continued)
Pin Name
Function
7
V_SS
Ground
8
SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9
SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
WP
Write Protect. WP HIGH prevents writes to any location in the device (includung all the registers).
It has an internal pull down resistor. (>10MΩ typical)
11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the V_TRIP3 voltage, V3FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a third power supply with no external components. Connect V3MON to V_SS or V_CC when
not used. The V3MON comparator is supplied by the V3MON input.
12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than V_TRIP3 and
goes HIGH when V3MON exceeds V_TRIP3. There is no power up reset delay circuitry on this pin.
13
WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
14
V_CC
Supply Voltage.
PRINCIPLES OF OPERATION
Power On Reset
Applying power to the X40030, X40031, X40034,
X40035 activates a Power On Reset Circuit that pulls
the RESET/RESET pins active. This signal provides
several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V_CC exceeds the device V_TRIP1 threshold value
for t_PURST (selectable) the circuit releases the RESET
(X40031, X40035) and RESET (X40030, X40034) pin
allowing the system to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
X40030/34
V_CC
System
Reset
RESET
MR
Manual
Reset
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for t_PURST there-
after.
Low Voltage V_CC (V1 Monitoring)
During operation, the X40030, X40031, X40034,
X40035 monitors the V_CC level and asserts
RESET/RESET if supply voltage falls below a preset
minimum V_TRIP1. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
remains active until V_CC returns and exceeds V_TRIP1
for t_PURST.
Low Voltage V2 Monitoring
The X40030 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V_TRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure.
For the X40030 and X40031 the V2FAIL signal
remains active until the V2MON drops below 1V
(V2MON falling). It also remains active until V2MON
6
FN8114.1
May 25, 2006