X40030_06 Datasheet, PDF (5/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
Device
Expected System
Voltages
V_trip1
(V)
X40030, X40031
-A
-B
-C
5V; 3V or 3.3V; 1.8V
5V; 3V; 1.8V
3.3V; 2.5V; 1.8V
2.0-4.75*
4.55-4.65*
4.35-4.45*
2.95-3.05*
X40034, X40035
-A
-B
-C
5V; 3.3V; 1.5V
5V; 3V or 3.3V; 1.5V
5V; 3V or 3.3V; 1.2V
2.0-4.75*
4.55-4.65*
4.55-4.65*
4.55-4.65*
*Voltage monitor requires V_CC to operate. Others are independent of V_CC
PIN CONFIGURATION
X40030, X40034
14-Pin SOIC, TSSOP
V2FAIL 1
V2MON ₂
LOWLINE 3
NC 4
14 V_CC
13 WDO
12 V3FAIL
11 V3MON
MR 5
RESET 6
V_{SS 7}
10 WP
9 SCL
8 SDA
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
V_trip2
(V)
1.70-4.75
2.85-2.95
2.55-2.65
2.15-2.25
0.90-3.50
1.25-1.35
1.25-1.35
0.95-1.05
V_trip3
(V)
1.70-4.75
1.65-1.75
1.65-1.75
1.65-1.75
1.70-4.75
3.05-3.15
2.85-2.95
2.85-2.95
POR
(system)
RESET = X40030
RESET = X40031
RESET = X40030
RESET = X40031
X40031, X40035
14-Pin SOIC, TSSOP
V2FAIL 1
V2MON ₂
LOWLINE 3
NC 4
14 ^VCC
13 WDO
12 V3FAIL
11 V3MON
MR ₅
RESET ₆
V_{SS 7}
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1
V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V_TRIP2 and
goes HIGH when V2MON exceeds V_TRIP2. There is no power up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the V_TRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V_SS or V_CC when
not used. The V2MON comparator is supplied by V2MON (X40030, X40031) or by the V_CC input
(X40034, X40035).
3 LOWLINE Early Low V_CC Detect. This CMOS output signal goes LOW when V_CC < V_TRIP1 and goes high
when V_CC > V_TRIP1.
4
NC
No connect.
5
MR
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t_PURST thereafter.
6 RESET/ RESET Output. (X40031, X40035) This open drain pin is an active LOW output which goes LOW
RESET
whenever V_CC falls below V_TRIP1 voltage or if manual reset is asserted. This output stays active
for the programmed time period (t_PURST) on power up. It will also stay active until manual reset is
released and for t_PURST thereafter.
RESET Output. (X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH
whenever V_CC falls below V_TRIP1 voltage or if manual reset is asserted. This output stays active
for the programmed time period (t_PURST) on power up. It will also stay active until manual reset is
released and for t_PURST thereafter.
5
FN8114.1
May 25, 2006