X40030_06 Datasheet, PDF (15/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
SERIAL DEVICE ADDRESSING
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘1011’.
– one bit (AS) that provides the device select bit. AS
bit is set-to “0” as factory default.
– next bit is ‘0’.
Figure 12. X40030, X40031, X40034, X40035
Addressing
Slave Byte
Control Register
1 0 1 1 0 0 1 R/W
Fault Detection Register 1 0 1 1 0 0 0 R/W
Control Register
Word Address
1 1 11 1 11 1
Fault Detection Register 1 1 1 1 1 1 1 1
– last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for t_PURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
15
FN8114.1
May 25, 2006