X40030_06 Datasheet, PDF (10/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
Figure 6. V_TRIPX Set/Reset Sequence (X = 1, 2, 3)
V_TRIPX Programming
No
Desired
V_TRIPX<
Present Value
YES
Execute
V_TRIPX Reset Sequence
Set V_X = desired V_TRIPX
Vx = V_CC, VxMON
Note: X = 1, 2, 3
Let: MDE = Maximum Desired Error
MDE⁺
Desired Value
MDE^–
Acceptable
Error Range
Error = Actual - Desired
New V_X applied =
Old V_X applied + | Error |
NO
Execute
Set Higher V_X Sequence
Apply V_CC and Voltage
> Desired V_TRIPX to V_X
Decrease V_X
New V_X applied =
Old V_X applied - | Error |
Execute Reset V_TRIPX
Sequence
Error < MDE^–
Output Switches?
YES
Actual V_{TRIPX -}
Desired ^VTRIPX
Error > MDE⁺
| Error | < | MDE |
DONE
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
PUP1, PUP0: Power Up Bits (Nonvolatile)
The Power Up bits, PUP1 and PUP0, determine the
t_PURST time delay. The nominal power up times are
shown in the following table.
PUP1
0
0
1
1
PUP0
0
1
0
1
Power on Reset Delay (t_PURST)
50ms
200ms (factory setting)
400ms
800ms
10
FN8114.1
May 25, 2006