X40030_06 Datasheet, PDF (18/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
V_CC = 5V
5V
V_CC
V2MON, V3MON
SDA
2.06kΩ
30pF
RESET
WDO
4.6kΩ
4.6kΩ
V2FAIL,
V3FAIL
30pF
30pF
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
Standard output load
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
A.C. CHARACTERISTICS
Symbol
Parameter
f_SCL
t_IN
t_AA
t_BUF
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_DH
t_R
t_F
t_SU:WP
t_HD:WP
Cb
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
Note: (1) Cb = total capacitance of one bus line in pF
Min.
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb⁽¹⁾
20 +.1Cb⁽¹⁾
0.6
0
Max.
400
0.9
300
300
400
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
18
FN8114.1
May 25, 2006