X40030_06 Datasheet, PDF (14/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor

X40030, X40031, X40034, X40035
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 10.
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Read Operation
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start con-
dition and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 11 for the
address, acknowledge, and data transfer sequence.
Figure 10. Acknowledge Polling Sequence
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK
Returned?
YES
High Voltage Cycle
Complete. Continue
Command Sequence?
YES
Continue Normal
Read or Write
Command Sequence
Issue STOP
NO
PROCEED
Figure 11. Random Address Read Sequence
S
S
Signals from ^t
Slave
the Master
a
r
Address
Byte
Address
t
Slave
a _Address
r
S
t
o
t
t
p
SDA Bus
10 1 10 0 0 1 1 11 11 1 1
1
Signals from
the Slave
A
A
C
C
K
K
A
C
K
Data
14
FN8114.1
May 25, 2006