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X40030_06 Datasheet, PDF (21/24 Pages) Intersil Corporation – Triple Voltage Monitor with Integrated CPU Supervisor
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X40030, X40031, X40034, X40035
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V)
Symbol
tRPD1(2)
tRPDL
t LR
tRPDX(2)
tPURST
Parameters
VTRIP1 to RESET/RESET (Power down only)
VTRIP1 to LOWLINE
LOWLINE to RESET/RESET delay (Power down only) [= tRPD1-tRPDL]
VTRIP2 to V2FAIL, or VTRIP3 to V3FAIL (x = 2, 3)
Power On Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory setting)
PUP1=1, PUP0=0
PUP1=1, PUP0=1
Min. Typ.(1)
500
50(2)
200
400(2)
800(2)
Max.
5
5
Unit
µs
ns
µs
ms
ms
ms
ms
tF
tR
VRVALID
tMD
tin1
tWDO
VCC, V2MON, V3MON, Fall Time
VCC, V2MON, V3MON, Rise Time
Reset Valid VCC
MR to RESET/ RESET delay (activation only)
Pulse width for MR
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
WD1=1, WD0=0
WD1 = 1, WD0 = 1 (factory setting)
20
20
1
500
5
1.4(2)
200(2)
25
OFF
mV/µs
mV/µs
V
ns
µs
s
ms
ms
tRST1
Watchdog Reset Time Out Delay
WD1=0, WD0=0
WD1=0, WD0=1
100 200 300
ms
tRST2 Watchdog Reset Time Out Delay WD1=1, WD0=0
tRSP Watchdog timer restart pulse width
Notes: (1) VCC = 5V at 25°C.
12.5 25
37.5
ms
1
µs
(2) Values based on characterization data only.
Watchdog Time Out for 2-Wire Interface
SCL
Start
Clockin (0 or 1)
tRSP
Start
< tWDO
SDA
WDO
Start
Minimum Sequence to Reset WDT
SCL
SDA
WDT
Restart
tRST tWDO tRST
21
FN8114.1
May 25, 2006
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