ISL6398 Datasheet, PDF (54/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
TABLE 19. PIN DESIGN AND/OR LAYOUT CONSIDERATION (Continued)
PIN NAME
NOISE
SENSITIVE
DESCRIPTION
VSEN_OVP
Yes Used for Overvoltage protection sensing.
VRSEL_ADDR
NVM_BANK_BT
No Register setting is locked prior to soft-
start. Since the external resistor-divider
ratio compares with the internal resistor
ratio of the V_CC, their rail should be
exactly tied to the same point as V_CC pin,
not through an RC filter. DON’T use
decoupling capacitors on these pins.
VR_RDY
No Open drain and high dv/dt pin. Avoid its
pull-up higher than V_CC. Tie it to ground
when not used.
IMON
Yes Refer to GND, not RGND. Place R and C in
general proximity to the controller. The
time constant of RC should be sufficient,
typically 200µs, as an averaging function
for the digital IOUT.
VR_HOT#
No Open drain and high dv/dt pin during
transitions. Avoid its pull-up rail higher
than V_CC . 30 mils spacing from other
traces.
SM_PM_I2CL
SM_PM_I2DA
Yes 50kHz to 1.5MHz signal when the SMBus,
PMBus, or I²C is sending commands,
pairing up with PMALERT# and routing
carefully back to SMBus, PMBus or I²C.
20 mils spacing within I2DATA,
PMALERT#, and I2CLK; and more than 30
mils to all other signals. Refer to the
SMBus, PMBus or I²C design guidelines
and place proper terminated (pull-up)
resistance for impedance matching.
Ground them when not used.
PMALERT#
No Open drain and high dv/dt pin during
transitions. Route it in the middle of
I2DATA and I2LK. Also see above. Leave it
open or tie it ground when not used.
BUF_COMP
Yes Buffer output of internal Comp Signal.
TM_EN_OTP
AUTO
Yes Place NTC in close proximity to the output
inductor of Channel 1 and to the output
rail, not close to MOSFET side (see Figure
24); the return trace should be 25 mils
away from other traces. Place 1k pull-
up and decoupling capacitor (typically
0.1µF) in close proximity to the controller.
The pull-up resistor should be exactly tied
to the same point as V_CC pin, not through
an RC filter. If not used, connect this pin to
1M /2M  resistor divider, or tie to V_CC .
Yes Program AUTO phase shedding threshold
a resistor from this pin to GND. AUTO
phase shedding is disabled when this pin
tied to GND.
RSET
Yes Place the R in close proximity to the
controller. DON’T use decoupling
capacitor on this pin.
TABLE 19. PIN DESIGN AND/OR LAYOUT CONSIDERATION (Continued)
PIN NAME
NOISE
SENSITIVE
DESCRIPTION
V_CC
Yes Place a high quality ceramic capacitor
(~ 1µF) in close proximity to the
controller.
PWM1-6
NO Avoid the respective PWM routing across
or under other phase’s power
trains/planes and current sensing
network. Don’t make them across or
under external components of the
controller. Keep them at least 20mils
away from any other traces.
ISEN[6:1]+
Yes Connect to the output rail side of the
respective channel’s output inductor or
resistor pin. Decoupling is optional and
might be required for long sense traces
and a poor layout.
ISEN[6:1]-
Yes Connect to the phase node side of the
respective channel’s output inductor or
resistor pin with L/DCR or ESL/R_SEN
matching network in close proximity to
the ISEN± pins of VR. Differentially
routing back to the controller by paring
with respective ISEN+; at least 20 mils
spacing between pairs and away from
other traces. Each pair should not cross or
go under the other channel’s switching
nodes [PHASE, UGATE, LGATE] and power
planes even though they are not in the
same layer.
GND
Yes This EPAD is the return of PWM output
drivers and PMBus. Use 4 or more vias to
directly connect the EPAD to the power
ground plane. Avoid using only single via
or 0Ω resistor connection to the power
ground plane. Also connect pins 13, 14
and 15 to ground plane.
General
Comments
The layer next to the Top or Bottom layer
is preferred to be ground players, while
the signal layers can be sandwiched in
the ground layers if possible.
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FN8575.1
August 13, 2015