ISL6398 Datasheet, PDF (53/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
0.3 _{IL(P-P) = 0}
I_L(P-P) = 0.25 I_O
0.2
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_OUT/V_IN)
FIGURE 39. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR 4-PHASE CONVERTER
Figures 38 and 39 provide the same input RMS current
information for 3 and 4-phase designs respectively. Use the
same approach to selecting the bulk capacitor type and number
as previously described.
Low capacitance, high-frequency ceramic capacitors are needed
in addition to the bulk capacitors to suppress leading and falling
edge voltage spikes. The result from the high current slew rates
produced by the upper MOSFETs turn on and off. Select low ESL
ceramic capacitors and place one as close as possible to each
upper MOSFET drain to minimize board parasitic impedances
and maximize noise suppression.
0.6
0.4
0.2
I_L(P-P) = 0
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
00
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_OUT/V_IN)
FIGURE 40. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR SINGLE-PHASE CONVERTER
MULTIPHASE RMS IMPROVEMENT
Figure 40 is provided as a reference to demonstrate the dramatic
reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a 2-phase
converter versus that of a single phase. Assume both converters
have a duty cycle of 0.25, maximum sustained output current of
40A, and a ratio of I_L,PP to I_O of 0.5. The single phase converter
would require 17.3A_RMS current capacity while the 2-phase
converter would only require 10.9A_RMS. The advantages become
even more pronounced when output current is increased and
additional phases are added to keep the component cost down
relative to the single phase approach.
Layout and Design Considerations
The following layout and design strategies are intended to minimize
the noise coupling, the impact of board parasitic impedances on
converter performance and to optimize the heat-dissipating
capabilities of the printed-circuit board. This section highlights some
important practices which should be followed during the layout
process. A layout check list is available for use.
Pin Noise Sensitivity, Design and Layout
Consideration
Table 19 shows the noise sensitivity of each pin and their design
and layout consideration. All pins and external components
should not be across switching nodes and should be placed in
general proximity to the controller.
TABLE 19. PIN DESIGN AND/OR LAYOUT CONSIDERATION
PIN NAME
NOISE
SENSITIVE
DESCRIPTION
ISENIN-
Yes Connect to input supply side of the input
inductor or resistor pin with L/DCR or
ESL/R matching network in close
proximity to the controller. Place NTC in
the close proximity to input inductor for
thermal compensation. A local 10nF
decoupling capacitor between ISENIN+
and ISENIN- is preferred. DCR sensing
with thermal compensation will yield no
load offset reading. Resistor sensing is
preferred for accurate input current
reporting. > 40 µs time constant
[C*R_IN1*R_IN2)/(R_IN1+R_IN2)] might
be needed if the average input
current reporting is preferred; and it
also reduces chance to trigger CFP
during heavy load transient.
ISENIN+
Yes Connects to the Drain of High-side
MOSFET side of the input inductor or
resistor pin. A local 0.1µF ceramic
capacitor is recommended. When not
used, connect ISENIN+ to V_IN and a
resistor divider with a ratio of 1/3 on
ISENIN± pin, say 499kΩ in between
ISENIN± pins and then 1.5MΩ from
ISENIN- to ground (see Figure 29). The
voltage of this pin is used feed-forward
compensation.
EN_PWR_CFP
Yes There is an internal 1µs filter. Decoupling
capacitor is NOT needed, but if needed,
use a low time constant one to avoid too
large a shut-down delay. It will also be the
output of CFP function: 34 strong
pull-up. 25 mils spacing from other
traces.
RGND
Yes Pair up (within 20 mils) with the positive
rail remote sensing line that connected to
FB resistor, and routing them to the load
sensing points.
VSEN
Yes Pair up (within 20 mils) with the negative
rail of remote sensing line that connected
to RGND, and route them to the load
sensing points.
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FN8575.1
August 13, 2015