ISL6398 Datasheet, PDF (34/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
TABLE 12. SYSTEM PARAMETER SUMMARY
CODE
PMBus
REG
DESCRIPTION
RANGE
PM_ADDR N/A
PMBus Address
80-8E, C0-CE,
E0-EE, F0-FE
VR_MODE N/A
By “VRSEL” pin
5mV or 10mVstep
5m Step Boot Voltage
0, 0.25 to 1.52V
BT
E6
10mV Step Boot Voltage 0, 0.5, 0.51 to 3.04V
F6
DVID Slew Rate
0.315 to 13.25mV/µs
DVID
D7 DVID UP Compensation Offset, Gain, Slope
D9 DVID Down Compensation Offset, Gain, Slope
TMAX E8
Maximum Operating
Temperature
+85°C to +120°C
(5°C/Step)
IMAX
NPSI
EA
I_CCMAX of Platforms
D2
Minimum Number of
Operational Phases in Auto
0-255A, 1A/LSB
SI1, SI2, CI1, CI2
D2
Frequency Limiter
2F_SW, 1.5F_SW, Infinity
E1
SET_UV
105mV to 402mV
D8
SET_OV
136mV to 549mV
24 Maximum Output Voltage
Up to 3.11V
Protection ^DF
F6
PROTECTION_DISABLE
INPUT OCP
All Faults
100% to 130%
E9
Thermal APA
75% to 100%
F4
AVG_OCP
CYCLE_LIMITING
1.0 TO 1.6
125% to 70%
F7-FC
Current Balance
-12% to +9%
DIGITAL ^E4
IOUT (8Ch) _E5
IMON_TRIM
IOUT_CAL_OFFSET
-4µA to +3.75µA
-4h to 3h
D8
UP Ramp Amplitude
0.75, 1.0, 1.2, 1.5V
DE
NVM_BANK
Up to 8 Banks
D4
Dither Enable
Enable or Disable
Mismatching Temperature
E9 Compensation between
sensing element and NTC
OFF, -2.5°C to
+35.1°C
LOOP
E2
PS Mode Transition
Compensation
PS Mode Transition
E2, E3
High Frequency Transient
Compensation
E2[4:3]: 20m- 80mV
E3: Phase Count
Original Speedup
F5
SET_FREQ
120k TO 2.025MHz
B0-BF
F3
COMPENSATION
SP_VdBand_K
R₁-R3 and C1-C3
Original, 2p-16pF
25mV - 200mV
0 to 0.75, Disable
TABLE 12. SYSTEM PARAMETER SUMMARY (Continued)
PMBus
CODE _REG
DESCRIPTION
RANGE
D6
LOCK_VID_OFFSET
0h to 3h
DA
Set_VID
up to 3.04V
DB
Output _D3
Voltage
Regulation ^D3
D3
Set_OFFSET
Droop Enable
Negative Droop
Positive Droop
up to 1.270V
Enable or Disable
100% to 5%
0mV, 4mV to 32mV
E4
IDROOP_TRIM
-4µA to +3.75µA
E4
Output Offset Trim
-4µA to +3.75µA
D0
NPHASE
1 TO 6-PHASE
D1
AUTO_K
1.0, 1.25, 1.5, 1.7
D1
AUTO_HYS
12.5, 16.6, 25, 50%
D1
AUTO_I1
80, 90, 100, 110%
D1
Minimum Phase
1 TO 4-PHASE
AUTO D2
AUTO Blanking
0.6ms to 4.6ms
D2
APA Time Constant
tsw/8 to tsw
D2
APA_Stackup_Delay
0 to 300ns
D4
APA LEVEL
10 to 70mV
D4
BOOT REFRESH
Enable or Disable
D4
AUTO Enable
Enable or Disable
99
MFR_ID
2 BYTES
9A
USER
9B
MFR_MODEL
MFR_REV
2 BYTES
2 BYTES
9D
MFR_DATE
3 BYTES
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FN8575.1
August 13, 2015