ISL6398 Datasheet, PDF (39/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
COMMAND
CODE
D1h[7:0]
ACCESS
R/W
D2h[9:0] R/W
D3h[6:0] R/W
D4h[6:0] R/W
D5h[1:0] R/W
D6h[1:0] R/W
D7h[13:0] BLOCK
R/W
TABLE 14. SMBus, PMBus, AND I²C WRITE AND READ REGISTERS
WRITE
PROTECT
LEVEL
DEFAULT
COMMAND NAME
DESCRIPTION
00h NVM_BANK
NMIN_AUTOK_HYS_I1
Bit[1:0] - Minimum Number of Auto Phase Shedding
0h = 1-Phase;1h = 2-Phase; 2h = 3-Phase; 3h = 4-Phase; Default
by N_PSI
Bit[3:2] - AUTO Mode K Factor:
0h = 1.25; 1h = 1.5; 2h = 1.75; 3h = 1.0; Default by AUTO pin
Bit[5:4] - AUTO Mode Hysteresis Factor
0h = 50%; 1h = 25%; 2h = 16.6%; 3h = 12.5%; Default by AUTO pin
Bit[7:6] - AUTO Mode I1 Factor:
0h = 100%; 1h = 80%; 2h = 90%; 3h = 110% of AUTO pin
00h NVM_BANK NPSI_AUTOBLK_FLIMITER_APATC Bit[1:0] - Lower Power Phase Number:
0h = SI1, 1-Phase;
1h = SI2, 2-Phase;
2h = CI1, 1-Phase;
3h = CI2, 2-Phase;
Bit[3:2] - Time between subsequent phase drops:
0h = 4.6ms; 1h = 2.3ms; 2h = 1.2ms; 3h = 0.6ms, Default 0h
Bit[5:4] - Maximum PWM frequency under repetitive Load:
0h = 2 F_SW; 1h = 3/2 F_SW; 2h = 3h = Infinity; Default 0h
Bit[7:6] - APA Time Constant:
0h = Tsw; 1h = Tsw/2; 2h = Tsw/4; 3h = Tsw/8. Default 3h
Bit[9:8] - APA Stackup Delay:
0h = 0ns; 1h=100ns; 2h = 200ns; 3h = 300ns
10h NVM_BANK
NEGLL_POSLL
Bit[0] - Droop Enable:
0h = Disabled, 1h = Enabled;
Bit[3:1] Droop Trim (NEGLL) of Full Scale:
0h = 100%, 1h = 75%, 2h =5 0%, 3h = 25%, 4h = 5%
Adjust R₁ for finer resolution
Bit[4]: Positive Load Line Enable:
0h = Disabled; 1h = Enabled
Bit[6:5]: Positive Load Line Range (POSLL):
0h = 4mV, 1h = 8mV; 2h = 16mV, 3h = 32mV at IMON Full Scale
10h NVM_BANK BTR_DE_AUTO_DITHER_APALVL Bit[0] - Boot-Refresh Enable:
0h = Disabled; 1h = Enabled. Boot refresh circuits is
automatically turned off when DAC is lower than 0.605V
Bit[1] - Diode Emulation Enable
0h = Disabled; 1h = Enabled
Bit[2] - AUTO Enable:
0h = Disabled; 1h = Enabled
Bit[3] - DITHER Enable:
0h = OFF, 1h = -15kHz, 0, 15kHz
Bit[6:4] - APA Level:
0h = Disable; 1h = 10mV; 2h = 20mV; 3h = 30mV; 4h = 40mV;
5h = 50mV; 6h = 60mV; 7h = 70mV
00h NVM_BANK
PWMTRI-LEVEL
Bit[0] - PWM Support: 0h = Compatible with 3.3V PWM Tri-State
(Mid) Level (PWM High is still V_CC, 5V); 1h = Compatible with
5.0V PWM Tri-State (Mid) Level. 5.0V PWM Driver is also
compatible with “0h”, but not vice versa.
20h
00h
LOCK_VID_OFFSET
Secondary output voltage control protection:
0h= VID and OFFSET NOT CONTROLLABLE
1h = Program Small OFFSET, not VID allowed
2h = Program Large OFFSET, not VID allowed
3h = VID and OFFSET CONTROLLABLE
(see Table 16 for details)
10h NVM_BANK
DVID_UP_OS_GAIN_SLP
BIT[5:0] - DVID_UP_OFFSET
00h = 0mV
01h = 5mV
02h = 10mV
…
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FN8575.1
August 13, 2015