ISL6398 Datasheet, PDF (25/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
When all conditions previously mentioned are satisfied, the
ISL6398 begins the soft-start and ramps the output voltage to
the Boot Voltage set by hard-wired “BT” registers. After remaining
at the boot voltage for some time, the ISL6398 reads the VID
code. If the VID code is valid, ISL6398 will regulate the output to
the final VID setting. If the VID code is “OFF” code, ISL6398 will
remain shut down.
ISL6398
EXTERNAL CIRCUIT
V_CC
+12V
t_D4 = -V---D-^V---V-^I--^D--I--D-^–----V-R----^B-A--^O--T---^O-E---^T-- s
(EQ. 15)
For example, when the V_BOOT is set at 1.1V and DVID slew rate is
set at 5mV/µs, the first soft-start ramp time t_D2 will be around
220µs and the second soft-start ramp time t_D4 will be at
maximum of 80µs if an SET_VID command for 1.5V is received
after t_D3.
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
100kΩ
EN_PWR_CFP
9.09kΩ
VCC
0.85V
1kΩ
TM_EN_OTP
+
-
1.08V
6.8kΩ
NTC
SOFT-START
AND
FAULT LOGIC
FIGURE 14. POWER SEQUENCING USING THRESHOLD-SENSITIVE
ENABLE (EN) FUNCTION
Soft-start
The ISL6398 based VR has 4 periods during soft-start, as shown in
Figure 15. After V_CC, TM_EN_OTP and EN_PWR_CFP reach their
POR/enable thresholds and the NVM_BANK loading time (typically
16ms, and worst case 20ms) expired, the controller will have a fixed
delay period t_D1. After this delay period, the VR will begin first soft-
start ramp until the output voltage reaches the V_BOOT voltage at a
fixed slew rate, as in Table 5. Then, the controller will regulate the VR
voltage at V_BOOT for another period t_D3 until PMBus sends a new
VID command. If the VID code is valid, ISL6398 will initiate the
second soft-start ramp at a slew rate, set by DVID command in
Table 5, until the voltage reaches the new VID voltage. The soft-start
time is the sum of the 4 periods, as shown in Equation 13.
t_SS = t_D1 + t_D2 + t_D3 + t_D4
(EQ. 13)
t_D1 is a fixed delay with the typical value as 20µs. t_D3 is determined
by the time to obtain a new valid VID voltage from PMBus. If the VID
is valid before the output reaches the boot voltage, the output will
turn around to respond to the new VID code.
During t_D2 and t_D4, the ISL6398 digitally controls the DAC
voltage change at 5mV per step. The soft-start ramp time t_D2
and t_D4 can be calculated based on Equations 14 and 15:
t_D2 = _{D-----V-V----I-}^B-D---^O--R--^O--A---^T-T----E-- s
(EQ. 14)
t_D1
t_D2 t_D3 t_D4
TM_EN_OTP
VR_Ready
FIGURE 15. SOFT-START WAVEFORMS
Current Sense Output
The current flowing out of the IMON pin is equal to the sensed
average current inside the ISL6398. In typical applications, a
resistor is placed from the IMON pin to GND to generate a
voltage, which is proportional to the load current and the resistor
value, as shown in Equation 16:
V_IMON = --R----^I--^M-N----^O----^N--- _R-----I^R--_S---^X-_E----_N-- I_LOAD
(EQ. 16)
where V_IMON is the voltage at the IMON pin, R_IMON is the resistor
between the IMON pin and GND, I_LOAD is the total output current
of the converter, R_ISEN is the sense resistor connected to the
ISEN+ pin, N is the active channel number, and R_X is the DC
resistance of the current sense element, either the DCR of the
inductor or R_SENSE depending on the sensing method.
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is typically 2.5V at the
maximum load current, typically corresponding to the I_CCMAX
register. The IMON voltage is linearly digitized every 88µs and
stored in the READ_IOUT register (8Ch). When the IMON voltage
reaches 2.5V or higher, the digitized I_OUT will reach the
maximum value of ICCMAX and the SM_PMALERT# pin is pulled
low.
R_IMON = ^{2----.--5---V----R--R--}_X---^I-^S----^E----^N-- _I--C-----_C----_{_}---_M----N-_A----_X----_{_}---₂---₁---_h--
(EQ. 17)
A small capacitor can be placed between the IMON pin and GND
to reduce the noise impact and provide averaging. If this pin is
not used, tie it to GND.
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FN8575.1
August 13, 2015