ISL6398 Datasheet, PDF (20/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
As explained in application note, AN1268 the leakage inductance
(not self inductance or mutual inductance) of the coupled
inductor should be used as the inductance in the time constant
calculation. Therefore, the leakage, self, and mutual inductance
should be well controlled for a good coupled inductor design.
Channel-current Balance
The sensed current I_n from each active channel is summed
together and divided by the number of active channels. The
resulting average current I_AVG provides a measure of the total
load current. Channel current balance is achieved by comparing
the sensed current of each channel to the average current to
make an appropriate adjustment to the PWM duty cycle of each
channel with Intersil’s patented current-balance method.
Channel current balance is essential in achieving the thermal
advantage of multiphase operation. With good current balance,
the power loss is equally dissipated over multiple devices and a
greater area. The ISL6398 can adjust the thermal/current
balance of the VR via registers F7 to FC.
Voltage Regulation (5mV and 10mV Mode)
The compensation network shown in Figure 11 assures that the
steady-state error in the output voltage is limited only to the error
in the reference voltage (DAC and OFFSET) and droop current
source, remote sense, and error amplifier.
The sensed average current I_DROOP is tied to FB internally and
will develop a voltage drop across the resistor between FB and
V_OUT for droop control. This current can be disconnected from the
FB node via PMBus for non-droop applications.
The output of the error amplifier, V_COMP, is compared to the internal
sawtooth waveforms to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and regulate
the converter output to the specified reference voltage.
For remote sensing, connect the load sensing pins to the
non-inverting input, VSEN, and inverting input, RGND, of the error
amplifier. This configuration effectively removes the voltage error
encountered when measuring the output voltage relative to the local
controller ground reference point.
COMPENSATION
DIGITALLY PROGRAMMABLE VIA PMBUS
VSEN
RGND
INPUT
BUFFER
C3
R3
RFB = R1
VOFFSET TRIM
(E4[9:5])
IDROOP
VOFFSET Trim
(E4[4:0])
DROOP
ENABLE
C2
R2
C1
FB
DAC
COMP
VID+OFFSET
BUF_COMP
FIGURE 11. OUTPUT VOLTAGE AND LOAD-LINE REGULATION
A digital-to-analog converter (DAC) generates a reference voltage,
which is programmable via PMBus bus. The DAC decodes the
PMBus set VID command into one of the discrete voltages shown
in Table 4. In addition, the output voltage can be margined in
±5mV step between -640mV and 635mV, ±10mV step between
-1280mV and 1270mV, as shown in Table 4. For a finer than 5mV
or 10mV offset, a large ratio resistor divider can be placed on the
VSEN pin between the output and GND for positive offset or V_CC
for negative offset, as in Figure 12. The VR operational mode is
programmed by the “VRSEL_ADDR” pin. Table 3 shows the
difference between 5mV and 10mV modes. VOUT_MAX and
VBOOT registers must be programmed accordingly to support
each mode, otherwise, the VR might NOT power-up correctly.
Furthermore, the PMBus register (E4h[9:5]) can program the
additional droop current (range from -4µA to 3.75µA) into R₁ for
DC offset calibration; a negative current will yield a negative
offset, while a positive current will yield a positive offset:
OFFSET = R₁* I(E4[9:5]). In droop applications, E4[4:0] can add
current out of IMON pin and droop current through R₁
simultaneously (the negative current yields positive offset, and
vice versa).
TABLE 3. 5mV vs 10mV DAC Resolution
MODE MAXIMUM VOUT_MAX
(VRSEL) DAC (V)
(24h)
MAXIMUM
VBOOT
(“BT” pin)
MAXIMUM
VBOOT
(E6)
5mV
2.155
Table 18
1.50
1.52
10mV
3.011
Table 4
Follow DAC
3.00
3.04
V_OUT
VSEN
+
-
V_OUT
V_CC
VSEN
+
-
DAC = VID+OFFSET
DAC = VID+OFFSET
A. V_OUT HIGHER THAN DAC
B. V_OUT LOWER THAN DAC
FIGURE 12. EXTERNAL PROGRAMMABLE REGULATION
TABLE 4. 5mV OR 10mV VID 8-BIT
HEX
BINARY CODE CODE
00000000 0
00000001 1
00000010 2
00000011 3
00000100 4
00000101 5
00000110 6
00000111 7
00001000 8
00001001 9
00001010 A
00001011 B
00001100 C
00001101 D
5mV
VID (V)
OFF
0.250
0.255
0.260
0.265
0.270
0.275
0.280
0.285
0.290
0.295
0.300
0.305
0.310
10mV
5mV
10mV
VID (V) OFFSET (mV) OFFSET (mV)
OFF
0
0
0.500
5
10
0.510
10
20
0.520
15
30
0.530
20
40
0.540
25
50
0.550
30
60
0.560
35
70
0.570
40
80
0.580
45
90
0.590
50
100
0.600
55
110
0.610
60
120
0.620
65
130
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August 13, 2015