ISL5216_14 Datasheet, PDF (51/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
Electrical Specifications V_CC1 = Core Supply: 2.5V ± 0.125V, V_CC2 = I/O Supply: 3.3 ± 0.165V ,
T_A = -40°C to +85°C Industrial (Continued)
PARAMETER
SYMBOL
MIN
MAX
UNITS
R/W Hold Time from Rising Edge of DSTRB
SERIAL CLOCK OUTPUT TIMING (FIGURE 11)
t_R/WHR
0
-
ns
CLK to Serial Data, Sync and SCLK (Divide-by 2 thru 16 Modes)
t_PD
-
8
ns
CLK to SCLK (Divide-by 1 Mode, Note 25)
t_PDL
-
6.5
ns
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 2 thru 16 Modes, Note 25) t_SKEW1
-2
2
ns
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 1 Mode, Note 25)
t_SKEW2
1
3
ns
NOTES:
24. The ISL5216 goes into reset immediately on RESET going low and comes out of reset on the 4th rising edge of CLK after RESET goes high.
25. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
AC Test Load Circuit
DUT
S₁
C_L (NOTE)
NOTE - TEST HEAD CAPACITANCE, 40pF (TYP)
SWITCH S1 OPEN FOR I_CCSB AND I_CCOP
±
I_OH
1.5V
I_OL
EQUIVALENT CIRCUIT
Waveforms
CLK
AIN, BIN, CIN, DIN, ENIA,
ENIB, ENIC, ENID, SYNCI,
SYNCI(0-3)
SYNCO, INTRPT
RESET
1/f_CLK
t_CH
t_CL
t_DS
t_DH
t_PDC
t_RW
t_RS
FIGURE 6. INPUT AND CONTROL TIMING
51
FN6013.3
July 13, 2007