ISL5216_14 Datasheet, PDF (30/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
Microprocessor Interface
15:0
M
U
31:16
31:0
INTERNAL READ DATA BUS
X
E
FROM OUTPUT FIFO
S
STATUS
RD
P(15:0)
WR
A(2:0)
CLK
CE
(GATING NOT SHOWN)
L
A
T
C
H
D ⁼⁰
E ₌₁
C
O = 2 or 3
D
E ⁼²
15:0
R
E
en
>G
31:16
R
E
en
>G
R
E
en
>G
RST
31:0
F
F
F
F
>F
>F
>F
>F
INTERNAL
WRITE DATA BUS
INTERNAL
ADDRESS BUS
AND
G
A
T ^SYNC’d
I ^WR
N
G
SPECIAL LOW
METASTABILITY
CELL
TO TARGET
REGISTERS
INTERNAL
READ SIGNAL
Data reads can be direct, indirect or FIFO-like depending on
the data that is being read. The status register is read
directly at direct (external) address 3, ADD(2:0) = 3.
Readback of internal registers and memories is indirect. The
16-bit indirect (internal) address of the desired read source
is first written to direct (external) address 3, ADD(2:0) = 3, to
select the data. The data can then be read at direct
(external) addresses ADD(2:0) = 0 and 1 (bits 15:0 at
address 0 and 31:16 at address 1). The data types available
via the indirect read are listed in the Tables of Indirect Read
Address (IRA) Registers. (Note that the μPHold bit contained
in the target register at Indirect Write Address (IWA) = *00Ah
must be set to suspend the filter compute engine before the
coefficient RAM and instruction bit fields can be written to or
read from.)
The ISL5216 output data from the four channels is available
through the microprocessor interface as well as from the
serial data outputs. A FIFO-like interface is used to read the
output data through the microprocessor interface. When new
output data is available, it is loaded into a FIFO in a user
programmed order (for details on the programming order
see Global Write Address (GWA) = F820h - F83Fh). It can
then be read, 16 bits at a time, at direct address 2, ADD(2:0)
= 2. At the end of each read, the FIFO counter is advanced
to the next location. This allows a DMA controller to read all
of the data with successive reads to a single direct address.
No writes or other interaction is required. The FIFO counter
is reset and reloaded by each interrupt signal, see GWA
F802h. New data in the FIFO is also indicated in the status
register located at direct address ADD(2:0) = 3 if a polled
mode is preferred. The eight data types available, for each of
the four channels, via this interface are: I(23:8), I(7:0)+8
Zeroes, Q(23:8), Q(7:0)+8 Zeroes, Mag(23:8), Mag(7:0)+8
Zeroes, Phase (15:0), and AGC (15:0). The upper bits of I,
i.e., I(23:8), and Q, i.e., Q(23:8), are not rounded to 16 bits.
This interface can read the data from all the channels that
are synchronized. However, because a common FIFO is
used and the FIFO is reset and reloaded by each interrupt, it
cannot be used for asynchronous channels.
The direct address map for the microprocessor interface is
shown in the Table of Microprocessor Direct Read/Write
Addresses and the procedures for reading and writing to this
interface are provided below. The bit field details for each
indirect read and write address is provided in the Table of
Indirect Read Address (IRA) Registers, Tables of Indirect
Write Address (IWA) Registers and Tables of Global Write
Address (GWA) Registers in the following sections.
30
FN6013.3
July 13, 2007