ISL5216_14 Datasheet, PDF (48/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
TABLE 50. TABLE OF INDIRECT READ ADDRESS (IRA) REGISTERS (Continued)
IRA
BITS
FUNCTION
*003h
5:0
CIC Destination FIR and Output Enable/Disable
*004h
19:0
Carrier NCO/CIC Control
*005h
31:0
Active Carrier NCO Center Frequency.
*007h
31:0
Timing NCO Frequency (upper 32 bits)
*008h
31:8
Timing NCO Frequency (lower 24 bits)
*00Ah
31:0
Filter Compute Engine/Resampler Control
*00Bh
13:0
Filter Start Offset
*00Ch
31:0
Wait Threshold/Decrement Value
*00Dh
8:0
Reset Write Pointer Offset
*00Eh
15:0
AGC gain load register (reads gain initially loaded into AGC gain register)
*00Fh
15:0
AGC gain read (must first write to AGC gain read strobe register IWA = *00Fh before reading)
*010h
31:0
AGC Loop Attack/Decay Gain Values
*011h
31:0
AGC Gain Limits
*012h
15:0
AGC Threshold
*013h
10:0
AGC/Discriminator Control
*014h
31:0
Serial Data Output Control
*015h
31:0
Serial Data Output 1 Content/Format (Register 1)
*016h
23:0
Serial Data Output 1 Content/Format (Register 2)
*017h
31:0
Serial Data Output 2 Content/Format (Register 1)
*018h
23:0
Serial Data Output 2 Content/Format (Register 2)
*01Ch
15:0
Carrier Phase Offset
*100h - *17Fh 31:0
Instruction RAMs.
*180h - *1FCh 30:0
Instruction RAMs (pointer RAM).
*400h - *43Fh 31:8
Coefficient ROM -HBF, const.
*440h - *47Fh 31:8
Coefficient RAM -1.
*480h - *4FFh 31:8
Coefficient RAM -2.
*500h - *5FFh 31:8
Coefficient ROM -Resampler.
F800h
31:0
Test Control
F801h
23:0
Bus Routing Control
F802h
31:0
Reset/SYNC/Interrupt Source Selection
F803h
31:0
Serial Clock Control
F804h
20:0
Input Level Detector Source Select
F805h
21:0
Input Level Detector Configuration
F806h
31:0
Input Level Detector result (valid when bit 1 of status word is set)
F807h
15:0
μP/Test Input Bus
F80Bh
31:0
BIST
F820h - F83Fh 4:0
μP FIFO Read Order Control
48
FN6013.3
July 13, 2007