ISL5216_14 Datasheet, PDF (2/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

Block Diagram
μP
TEST
REGISTER
INPUT SELECT,
FORMAT,
DEMUX
LEVEL
DETECTOR
ISL5216
A(15:-1)
ENIA
B(15:-1)
ENIB
C(15:-1)
ENIC
D(15:-1)
ENID
CLK
RESET
SYNCI
SYNCO
SYNCI0
SYNCI1
SYNCI2
SYNCI3
TRST
TCLK
TMS
TDI
TDO
INPUT SELECT,
FORMAT,
DEMUX
I
NCO/MIXER/CIC
Q
CHANNEL 0
FIR FILTERS,
AGC,
CARTESIAN-TO-POLAR
COORDINATE
CONVERTER
INPUT SELECT,
FORMAT,
DEMUX
INPUT SELECT,
FORMAT,
DEMUX
I
NCO/MIXER/CIC
Q
CHANNEL 1
I
NCO/MIXER/CIC
Q
BUS
ROUTING
CHANNEL 2
FIR FILTERS,
AGC,
CARTESIAN-TO-POLAR
COORDINATE
CONVERTER
FIR FILTERS,
AGC,
CARTESIAN-TO-POLAR
COORDINATE
CONVERTER
INPUT SELECT,
FORMAT,
DEMUX
I
NCO/MIXER/CIC
Q
CHANNEL 3
FIR FILTERS,
AGC,
CARTESIAN-TO-POLAR
COORDINATE
CONVERTER
SCLK
SYNCA
SD1A
SD2A
SYNCB
SD1B
SD2B
OUTPUT
SELECT,
FORMAT,
SERIALIZE
SYNCC
SD1C
SD2C
SYNCD
SD1D
SD2D
P(15:0)
ADD(2:0)
μP INTERFACE
RD
or
RD/WR
WR
or
DSTRB
μP MODE
INTRPT
CE
2
FN6013.3
July 13, 2007