ISL5216_14 Datasheet, PDF (44/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
P(31:0)
31:24
23:20
19:17
16
15:14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TABLE 38. BUS ROUTING CONTROL REGISTER (GWA = F801h)
FUNCTION
Unused - set to zero.
Interrupt pulse width. The width of the interrupt pulse at the pin can be programmed to be from 1 to 15 clocks wide. Program with the
desired number of clocks. (NOTE: The pulse counter is only reset with the RESET pin. If a channel is reset by software or a SYNCI,
any interrupt pulse in process will finish).
Set to 0.
CH1 or CH3 AGC to CH0 ext AGC. This bit selects whether the AGC loop filter output from CH1 or CH3 is routed to the external
AGC gain input of CH0. 0=CH3, 1=CH1.
CH3 ext source mux sel. These bits select whether the CH2 source mux, CIC2, or FIR2out is routed to the external input of FIR3.
0=CH2srcmux, 1=FIR2, 2=CIC2.
CH2 ext source mux sel. This bit selects whether the CH1 external source mux or FIR1out is routed to the external input of FIR2.
0=CH1srcmux, 1=FIR1out.
CH1 ext source mux sel. This bit selects whether the CIC0 output or FIR0out is routed to the external input of FIR1. 0=CIC0,
1=FIR0out.
Set to 0.
CH1 backend input sel 0=CIC1, 1=CH1 ext src mux.
CH2 backend input sel 0=CIC2, 1=CH2 ext src mux.
CH3 backend input sel 0=CIC3, 1=CH3 ext source mux.
CH0 Ext AGC input enable. 0=CH0 loop filt, 1=external input.
CH1 Ext AGC input enable 0=CH1 loop filt, 1=external input.
CH2 Ext AGC input enable 0=CH2 loop filt, 1=external input.
CH3 Ext AGC input enable Set to 0.
CH0 enable serial output 1=FIR0 out enabled to serial outputs.
CH1 enable serial output 1=FIR1 out enabled to serial outputs.
CH2 enable serial output 1=FIR2 out enabled to serial outputs.
CH3 enable serial output 1=FIR3 out enabled to serial outputs.
P(31:0)
31
30
29
28
27
26
25
24
23:16
15:8
7:0
TABLE 39. RESET/SYNC/INTERRUPT SOURCE SELECTION REGISTER (GWA = F802h)
FUNCTION
When set, an interrupt will be generated on each data output of channel 0 to the output block. Typically, this bit will only be set for
one channel.
When set, the data input to the part will be disabled (the input enable will be zeroed and held at zero) on a μP reset (this is always
true for the reset pin, whether this bit is set or not, and additionally, the reset pin sets the input mode to gated). The input enable will
be released for the input sample that aligns with the SYNCI signal. This is a method for starting up the processing synchronous with
a particular data sample.
When this bit is set, the carrier center frequency will be updated from the holding register (IWA = *005h) to the active register on the
SYNCI signal. If the bit is set in register IWA = *004h to clear the phase accumulator feedback on loading, this function will
synchronize the phase of multiple channels. After initial synchronization, the bit in IWA = *004h can be cleared and updates will be
synchronous and phase continuous across channels.
When this bit is set, the FIR filter compute engine is reset on SYNCI. Resetting the FIR filter compute engine requires 32 clock (CLK)
cycles to initialize the read and write pointers.
When this bit is set, the AGC is reset on SYNCI.
This bit has the same function as bit 29, but for the timing (resampler) NCO. The bit to zero the phase accumulator feedback is in
register IWA = *00Ah.
When this bit is set, the CIC decimation counter is reset on SYNCI.
When this bit is set, the serial output block is reset on SYNCI. If bit 4 in location GWA F803h is set, the serial clock divider is also reset.
Same functions as 31:24 for channel 1.
Same functions as 31:24 for channel 2.
Same functions as 31:24 for channel 3.
44
FN6013.3
July 13, 2007