ISL5216_14 Datasheet, PDF (37/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
P(15:0)
N/A
TABLE 11. CARRIER NCO CENTER FREQUENCY UPDATE STROBE REGISTER (IWA = *006h)
FUNCTION
Writing to this address generates a strobe that transfers the CCF value to the active frequency register. The transfer to the active
register can also be done using the SYNCI pin to synchronize the transfer in multiple parts or to synchronize to an external event.
P(31:0)
31:0
TABLE 12. TIMING NCO FREQUENCY CONTROL REGISTER, MSW (IWA = *007h)
FUNCTION
These are the upper 32 bits of the 56-bit timing (resampler) NCO center frequency control.
P(31:0)
31:8
7:0
TABLE 13. TIMING NCO FREQUENCY CONTROL REGISTER, LSW (IWA = *008h)
FUNCTION
These are the lower 24 bits of the 56-bit timing (resampler) NCO center frequency control.
Unused, set to zero.
P(31:0)
N/A
TABLE 14. TIMING NCO CENTER FREQUENCY LOAD STROBE REGISTER (IWA = *009h)
FUNCTION
A write to this location will update the resampler NCO center frequency.
P(31:0)
31
30
29
28:24
23
22
21:20
19
18
17
16
15
TABLE 15. FILTER COMPUTE ENGINE/RESAMPLER CONTROL REGISTER (IWA = *00Ah)
FUNCTION
μPHold. When set, this bit stops the filter compute engine and allows the μP access to the instruction and coefficient RAMs for
reading and writing. On the high to low transition, the filter compute engine is reset (the read and write pointers are reset and the
instruction at location 31 is fetched).
μPShiftZeroB. This bit, when set to zero, disables the coefficient shift bits (bits 9:8 of the master register when coefficient loading).
μPEN Limit. This bit disables the data path saturation logic. Provided for test. Active high. Set to 0 to disable the normal ROM
controlled limiting (ANDed with normal signal).
μPZ(4:0). These bits, when set to 0, zero the corresponding read pointer address bits. This allows the pointers to be aliased, i.e.,
multiple filters can access and/or modify the same pointer. They are provided to change filters, coefficients or decimation over a
sequence.
Unused, set to 0.
Timing (resampler) NCO ENsync. If this bit is set, the center frequency is updated on a SYNCI. Set to 1.
RSRVRS(1:0). Set to 01.
Beginning/End. This bit selects whether the resampler NCO is updated at the beginning of a FIR computation or at the end of each
FIR output computation. Usually, the resampler will be updated once at the beginning of each resampler computation and this will be
bit set to 1.
1 Once at the beginning of the FIR instruction.
0 At the last tap of each of the instruction’s FIR computations (once per output).
RSModeSelect. This bit selects whether the resampler is a phase shifter or a frequency shifter.
0 Phase shift. It uses the top five bits of the timing NCO frequency to determine a phase shift and disables feedback in the timing
NCO phase accumulator—effect of the resampler is a constant phase shift.
1 Frequency shift. Effect of the resampler is a change in the sample rate.
RSCO. This bit is provided to force the resampler NCO carry when using the resampler as a phase shifter rather than for a frequency
shift. This bit must be set for phase shifting and cleared for frequency shifting. (The bit is Or-ed with the normal carry.)
RS NCO clear phase accumulator feedback on load. When this bit is set, the feedback in the resampler NCO phase accumulator is
zeroed whenever the center frequency word is updated. This forces the NCO to a known phase so the phase of multiple channels
can be aligned.
Force NCO load. This bit, when set, zeroes the feedback in the resampler NCO phase accumulator. This is provided for test or to
use the resampler for phase instead of frequency shifting.
37
FN6013.3
July 13, 2007