ISL5216_14 Datasheet, PDF (34/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
Tables of Indirect Write Address (IWA) Registers
NOTE: These Indirect Write Addresses are repeated for each
channel. In the addresses below, the * field is the channel select
nibble. These bits of the Indirect Address select the target channel
register for the data. Values of 0 through 3 and F are valid. A channel
select nibble value of F is a special case which writes the data to the
same location in each of the four channels simultaneously.
TABLE 4. CHANNEL INPUT SELECT/FORMAT REGISTER (IWA = *000h)
P(31:0)
FUNCTION
24
Upper Side Band/Lower Side Band select for use in complex input mode.
23
For complex input mode: when set to 1, the I sample is taken when ENIX is active and the Q sample is taken on the next clock. When
set to 0, Q sample is taken two clocks after ENIX is active.
22
Complex input enable. Set to 1 for complex input mode, 0 for real input mode.
21
If set, adjusts the alignment between input data enables and NCO enables to allow unevenly spaced input samples in the gated input
mode. This may be set to 0 to align processing delays with the HSP50216 if necessary.
20:18
Floating point exponent saturation level. Used with floating point modes to set the maximum exponent code level 000 to 111. These
bits are protection against overflow due to an invalid exponent for the programmed CIC shift code. Set to 111 to disable.
17
Enables the new (ISL5216) floating point modes -- the 11, 12, 13 and 14-bit modes with 42 dB of gain, and 15 and 16-bit modes with
18 dB and 6 dB ranges, respectively. The X-1 input must be used for 14, 15 and 16-bit modes. See Floating Point Input Mode Bit
Mapping Tables for details.
16
Floating point mode select bit 2. Used with IWA *000, bits 8:7 to select the floating point mode/format. See Floating Point Input Mode
Bit Mapping Tables for details.
15:13
12
Channel Input Source Selection - Selects as the data input for the channel specified in the Indirect Address either A(15:0), B(15:0),
C(15:0), D(15:0) or the μP Test Input register as shown below:
15:13
SOURCE SELECTED
000
A(15:0)
001
B(15:0)
010
C(15:0)
011
D(15:0)
100
μP Test input register. This is provided for testing and to zero the input data bus when a channel is not in use.
The Global Write Address register for the μP Test input register is F807h.
μP Test Register input enable selection:
1
Bit 11 of this register is used as the input enable.
0
A one clock wide pulse generated on each write to lGWA F808h is used as the input enable.
Select 0 to write test data into the part.
Select 1 to input a constant or to disable the input for minimum power dissipation when an NCO/mixer/CIC section is unused.
11
μP input enable. When bit 12 is set, this bit is the input enable for the μP Test Register input. Active low:
0
Enabled
1
Disabled.
10
Parallel Data Input Format:
0
Two’s complement (-full scale = 1000...0000, zero = 0000...0000, +full scale = 0111...1111).
1
Offset binary (-full scale = 0000...0000, zero = 1000...0000, +full scale = 1111...1111).
9
Fixed/Floating point:
0
Fixed point.
1
Floating point. The 17-bit input bus is divided into 11 to 16 mantissa bits and 1 to 3 exponent bits depending on bits 17,
16, 8 and 7. See Floating Point Input Mode Bit Mapping Tables for details.
8:7
Floating point mantissa size select bits 0 and 1. See Floating Point Input Mode Bit Mapping Tables for details.
34
FN6013.3
July 13, 2007