ISL5216_14 Datasheet, PDF (47/65 Pages) Intersil Corporation – Four-Channel Programmable Digital Downconverter

ISL5216
P(15:0)
N/A
TABLE 45. μP/TEST INPUT BUS ENI REGISTER (GWA = F808h)
FUNCTION
A write to this location, generates and ENI strobe for the μP driven input port (when selected via bit 12 of IWA *000h).
P(15:0)
N/A
TABLE 46. SYNCO STROBE REGISTER (GWA = F809h)
FUNCTION
A write to this location will cause a one-clock-wide pulse on the SYNCO pin. The SYNCO pin is used to synchronize multiple channels
or parts. The SYNCO pin from one part is typically connected to the SYNCI pin of all the parts. Up to two pipeline registers may be
inserted in the SYNCO to SYNCI path.
P(15:0)
N/A
TABLE 47. SYNCI STROBE REGISTER (GWA = F80Ah)
A write to this location generates a SYNCO pulse but also feeds it back to the SYNCI input.
P(15:0)
15:0
TABLE 48. TEST CRC REGISTER (GWA = F80Bh)
Test CRC register. Load comparison signature into 15:0. Following a BIST test, the part returns its computed signature to 31:16.
P(15:0)
4:0
TABLE 49. μP FIFO READ ORDER CONTROL REGISTER (GWA = F820h thru F83Fh)
FUNCTION
The five bits selecting the data type are encoded as follows:
C C D D D,
where CC is the channel number and DDD is the data type.
DDD
Data Type
000 I(23:8)
001 I(7:0),8*zeros
010 Q(23:8)
011 Q(7:0),8*zero
100 Mag(23:8)
101 Mag(7:0),8*zero
110 Phase(15:0)
111 AGC gain (15:0)
The upper 16 bits of the I data path via the FIFO/AGC.
The lower 8 bits of the I data path.
The upper 16 bits of the Q data path via the FIFO/AGC.
The lower 8 bits of the Q data path.
The upper 16 bits of magnitude (after the gain adjust described in channel register)
The lower 8 bits of magnitude.
The upper 16 bits of phase.
The upper 16 bits of the AGC gain.
Table of Indirect Read Address (IRA) Registers
The address decoding for the read source locations is given
below. The internal address of the data to be read is written
to direct address 3 (ADD(2:0) = 3) to select and/or fetch the
data. A strobe is generated, if needed, to fetch or stabilize
the data for reading. If a strobe is needed, the indirect read
address must be written to direct address 3 each time the
data is needed. If a strobe is not needed, the data can be
read repeatedly at direct addresses 0 and 1(ADD(2:0) = 0
and 1, respectively) with any changes in the data showing up
immediately. The strobe to sample the AGC gain is
generated separately by an indirect write (see IWA *00Fh in
the Tables of Indirect Write Address Registers). This allows
the AGC gain of all the channels to be sampled
simultaneously. The indirect read address register is shared
with indirect write address register, so a data verification
read may be done immediately after a write without needing
to write the register address to ADD(2:0) = 3 again.
NOTE: These Indirect Read Addresses are repeated for each channel. In the addresses below, the * field is the channel select nibble. These bits
of the Indirect Address select the target channel register for the data being read. Values of 0 through 3 and F are valid.
IRA
*000h
*001h
*002h
BITS
24:0
15:0
15:0
TABLE 50. TABLE OF INDIRECT READ ADDRESS (IRA) REGISTERS
FUNCTION
Channel Input Select/Format
PN Gain
CIC Decimation
47
FN6013.3
July 13, 2007