ISL6363_14 Datasheet, PDF (4/32 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12™ Desktop CPUs

ISL6363
Pin Descriptions (Continued)
ISL6363
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SYMBOL
BOOT2
LGATE2
PVCC
LGATE1
BOOT1
UGATE1
PHASE1
ADDR
DESCRIPTION
Connect an MLCC capacitor from this pin to the PHASE2 pin. The boot capacitor is charged through an internal boot diode
connected from the PVCCG pin to the BOOTG pin.
Output of the VR1 phase 2 low-side MOSFET gate driver. Connect this pin to the gate of the low-side MOSFET of phase 2.
Input voltage bias for the internal gate drivers for VR1. Connect +12V to this pin. Decouple with at least a 1µF MLCC capacitor
and place it as close to the pin as possible.
Output of the VR1 phase 1 low-side MOSFET gate driver. Connect this pin to the gate of the low-side MOSFET of phase 1.
Connect an MLCC capacitor from this pin to the PHASE1 pin. The boot capacitor is charged through an internal boot diode
connected from the PVCC pin to the BOOT1 pin.
Output of the VR1 phase 1 high-side MOSFET gate drive. Connect this pin to the gate of the high-side MOSFET of phase 1.
Current return path for the VR1 phase 1 high-side MOSFET gate driver. Connect this pin to the node connecting the source of
the high-side MOSFET, the drain of the low-side MOSFET and the output inductor of phase 1.
A resistor from this pin to GND programs the SVID address for VR1 and VR2. Refer to Table 9 on page 28.
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FN6898.1
September 5, 2013