ISL6363_14 Datasheet, PDF (29/32 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12™ Desktop CPUs

ISL6363
NTC Network on the NTC and the NTCG pins
The controller drives 60µA current source out of the NTC pin and
the NTCG pin alternatively at 1kHz frequency with 50% duty
cycle. The current source flows through the respective NTC
resistor networks on the pins and creates voltages that are
monitored by the controller through an A/D converter to generate
the TZONE value. Table 10 shows the programming table for
TZONE. The user needs to scale the NTC (and NTCG) network
resistance such that it generates the NTC (and NTCG) pin voltage
that corresponds to the left-most column. Do not use any
capacitor to filter the voltage. On ADC Output = 7, the controller
issues thermal alert to the CPU, on ADC Output <7, the controller
asserts the VR_HOT# signal.
TABLE 10. TZONE PROGRAMMING TABLE
VNTC (V)
ADC OUTPUT
%TMAX
TZONE
0.64
0
>100%
FFh
0.68
1
>100%
FFh
0.72
2
>100%
FFh
0.76
3
>100%
FFh
0.80
4
>100%
FFh
0.84
5
>100%
FFh
0.88
6
100%
FFh
0.92
7
97%
7Fh
0.96
8
94%
3Fh
1.00
9
91%
1Fh
1.04
A
88%
0Fh
1.08
B
85%
07h
1.12
C
82%
03h
1.16
D
79%
01h
1.2
E
76%
01h
>1.2
F
<76%
00h
Current Monitor
Refer to Equation 18 for the IMON pin current expression.
Referencing the “Simplified Application Circuit” on page 6, the
IMON pin current flows through R_imon. The voltage across R_imon is
expressed in Equation 39:
V_Rimon = 3 × I_droop × R_imon
(EQ. 39)
Rewriting Equation 38 gives Equation 40:
I_droop
=
--------^I-^o---------
R_droop
×
LL
(EQ. 40)
Substitution of Equation 40 into Equation 39 gives Equation 41:
V_Rimon
=
3_----I_--o-----×_----L_----L_-
R_droop
×
R_imon
(EQ. 41)
Rewriting Equation 41 and application of full load condition gives
Equation 42:
R_imon = ^V----^R----ⁱ-^m---₃--^o--_I--^no----^××-----^RL----_L^d---^r--^o---^o----^p-
(EQ. 42)
For example, given LL = 1.9mΩ, R_droop = 2.825kΩ,
V_Rimon = 2.7V at I_omax = 53A, Equation 42 gives
R_imon = 25.2kΩ.
A capacitor C_imon can be paralleled with R_imon to filter the IMON
pin voltage. The R_imonC_imon time constant is the user’s choice. It
is recommended to have a time constant long enough such that
switching frequency ripples are removed.
Current Balancing
The ISL6363 achieves current balancing through matching the
ISEN pin voltages. R_isen and C_isen form filters to remove the
switching ripple of the phase node voltages. It is recommended
to use a rather long R_isenC_isen time constant such that the ISEN
voltages have minimal ripple and represent the DC current
flowing through the inductors. Recommended values are
R_s = 10kΩ and C_s = 0.22µF.
Optional Slew Rate Compensation Circuit for
1-Tick VID Transition
Rdroop
Rvid Cvid
FB
Ivid
Vcore
OPTIONAL
Idroop_vid
COMP
E/A
Σ
DAC
VDAC
X1
INTERNAL
TO IC
VIDs
VID<0:6>
RTN
VSSSENSE
VSS
VID<0:6>
Vfb
Ivid
Vcore
Idroop_vid
FIGURE 27. OPTIONAL SLEW RATE COMPENSATION CIRCUIT FOR
1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate. For example, the DAC may change a tick
(5mV) per 0.5µs, controlling output voltage V_CORE slew rate at
10mV/µs.
29
FN6898.1
September 5, 2013