ISL6363_14 Datasheet, PDF (22/32 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12™ Desktop CPUs

ISL6363
TABLE 6. SUPPORTED DATA AND CONFIGURATION
REGISTERS (Continued)
REGISTER
INDEX
NAME
DESCRIPTION
DEFAULT
VALUE
06h Capability
Identifies the SVID VR
81h
capabilities and which of the
optional telemetry registers are
supported.
10h Status_1
Data register read after ALERT# 00h
signal. Indicating if a VR rail has
settled, has reached VRHOT
condition or has reached ICC
max.
11h Status_2
Data register showing status_2 00h
communication.
12h Temperature Data register showing
00h
Zone
temperature zones that have
been entered.
1Ch Status_2_
LastRead
This register contains a copy of 00h
the Status_2 data that was last
read with the GetReg (Status_2)
command.
21h ICC max
Data register containing the ICC Refer to
max the platform supports, set Table 7
at start-up by resistors Rprog1
and Rprog2. The platform
design engineer programs this
value during the design process.
Binary format in amps, i.e.,
100A = 64h
22h Temp max
Data register containing the Refer to
temperature max the platform Table 8
support, set at startup by
resistor Rprog2. The platform
design engineer programs this
value during the design process.
Binary format in °C, i.e.,
+100°C = 64h
24h SR-fast
Slew Rate Normal. The fastest 0Ah
slew rate the platform VR can
sustain. Binary format in
mV/µs. i.e., 0Ah = 10mV/µs.
25h SR-slow
Is 4x slower than normal. Binary 02h
format in mV/µs. i.e.,
02h = 2.5mV/µs
26h V_BOOT
If programmed by the platform, 00h
the VR supports V_BOOT voltage
during start-up ramp. The VR will
ramp to V_BOOT and hold at
V_BOOT until it receives a new
SetVID command to move to a
different voltage.
30h Vout max
This register is programmed by FBh
the master and sets the
maximum VID the VR will
support. If a higher VID code is
received, the VR will respond
with “not supported”
acknowledge.
TABLE 6. SUPPORTED DATA AND CONFIGURATION
REGISTERS (Continued)
REGISTER
INDEX
NAME
DESCRIPTION
DEFAULT
VALUE
31h VID Setting Data register containing
00h
currently programmed VID
voltage. VID data format.
32h Power State Register containing the current 00h
programmed power state.
33h Voltage Offset Sets offset in VID steps added to 00h
the VID setting for voltage
margining. Bit 7 is a sign bit,
0 = positive margin,
1 = negative margin. Remaining
7 bits are # VID steps for the
margin.
00h = no margin,
01h = +1 VID step
02h = +2 VID steps
34h Multi VR Config Data register that configures VR1: 00h
multiple VRs behavior on the VR2: 01h
same SVID bus.
Key Component Selection
Inductor DCR Current-Sensing Network
Phase1 Phase2 Phase3
Rsum
Rsum
Rsum
ISUM+
L
L
L
DCR
DCR
DCR
Rntcs
Rp
Rntc
Ro
Ro
Ro
Cn Vcn
Ri ^ISUM-
Io
FIGURE 16. DCR CURRENT-SENSING NETWORK
Figure 16 shows the inductor DCR current-sensing network for a
3-phase solution. An inductor current flows through the DCR and
creates a voltage drop. Each inductor has two resistors in R_sum
and R_o connected to the pads to accurately sense the inductor
current by sensing the DCR voltage drop. The R_sum and R_o
resistors are connected in a summing network as shown, and feed
the total current information to the NTC network (consisting of
R_ntcs, R_ntc and R_p) and capacitor C_n. R_ntc is a negative
temperature coefficient (NTC) thermistor, used to
temperature-compensate the inductor DCR change.
The inductor output side pads are electrically shorted in the
schematic, but have some parasitic impedance in actual board
layout, which is why one cannot simply short them together for the
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FN6898.1
September 5, 2013