ISL6363_14 Datasheet, PDF (30/32 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12™ Desktop CPUs

ISL6363
Figure 27 shows the waveforms of 1-tick VID transition. During
1-tick VID transition, the DAC output changes at approximately
15mV/µs slew rate, but the DAC cannot step through multiple
VIDs to control the slew rate. Instead, the control loop response
speed determines V_CORE slew rate. Ideally, V_CORE will follow the
FB pin voltage slew rate. However, the controller senses the
inductor current increase during the up transition, as the
I_{droop_vid} waveform shows, and will droop the output voltage
V_CORE accordingly, making V_CORE slew rate slow. Similar
behavior occurs during the down transition.
To control V_CORE slew rate during 1-tick VID transition, one can
add the R_vid-C_vid branch, whose current I_vid cancels I_{droop_vid}.
When V_CORE increases, the time domain expression of the
induced I_droop change is:
I_droop(t)
=
-^C---^o---^u----^t---^×-----^L---^L-
R_droop
×
-^d---^V----^c---^o---^r--^e-
dt
×
⎛
⎜
⎜
1
⎝
–
e
C^----_o^----_u^---–-_t^--t-×^-----L^---L^--_⎟⎞
⎟
⎠
(EQ. 43)
Where C_out is the total output capacitance.
In the mean time, the R_vid-C_vid branch current I_vid time domain
expression is:
I_vid(t)
=
C_v
id
×
d_----V_----f--b-
dt
×
⎛
⎜
⎜
1
⎝
–
e ^{R-----v---i--d---–-×--t---C----v---i--d--}_{⎟⎟⎞}
⎠
(EQ. 44)
It is desired to let I_vid(t) cancel I_{droop_vid}(t). So there are:
C_v
id
×
d_----V_----f--b-
dt
=
-^C---^o---^u----^t---^×-----^L---^L- × -^d---^V----^c---^o---^r--^e-
R_droop
dt
(EQ. 45)
and:
R_vid × C_vid = C_out × LL
(EQ. 46)
The result is expressed in Equation 47:
R_vid = R_droop
(EQ. 47)
and:
C_vid
=
C_{----o---u----t---}×_-----L_---L_-
×
d_----V_{----c---o---r--e-}
-------^d----^t------
R_droop
d_----V_----f--b-
dt
(EQ. 48)
For example: given LL = 1.9mΩ, R_droop = 2.37kΩ,
C_out = 1320µF, dV_CORE/dt = 10mV/µs and dV_fb/dt = 15mV/µs,
Equation 47 gives R_vid = 2.37kΩ and Equation 48 gives
C_vid = 700pF.
It is recommended to select the calculated R_vid value and start
with the calculated C_vid value and tweak it on the actual board to
get the best performance.
During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The
R_vid - C_vid network is between the virtual ground and the real
ground, and hence has no effect on transient response.
30
FN6898.1
September 5, 2013