ISL6363_14 Datasheet, PDF (3/32 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12™ Desktop CPUs

ISL6363
Pin Descriptions (Continued)
ISL6363 SYMBOL
DESCRIPTION
9
ISEN4 VR1 phase 4 current sense input pin for phase current balancing.
10
VSEN VR1 remote core voltage sense input.
11
PSICOMP This pin is used for improving transient response in PS2/3 mode of VR1 by switching in an additional type 3 compensation
network to improve system gain and phase margin. Connect a resistor and capacitor from this pin to the output of VR1 near
the feedback compensation network.
12
RTN VR1 remote voltage sensing return input. Connect this pin to the remote ground sensing location.
13
FB
Inverting input of the error amplifier for VR1.
14
COMP This is a dual function pin. This pin is the output of the error amplifier for VR1. A resistor connected from this pin to GND
programs IMAX for VR1 and V_BOOT for both VR1 and VR2. Refer to Table 7 on page 28.
15
VW
A resistor from this pin to COMP programs the PWM switching frequency for VR1.
16
NTC One of the thermistor network inputs to the thermal monitoring circuit used to control the VR_HOT# signal. Use this pin to
monitor the temperature of VR1. Place the NTC close to the desired thermal detection point on the PCB.
17
IMON Current monitoring output pin for VR1. The current sense signal from ISUMN and ISUMP is output on this pin to generate a
voltage proportional to the output current of VR1.
18
VR_ON Enable input signal for the controller. A high level logic signal on this pin enables the controller and initiates soft-start for VR1
and VR2.
19, 20, 21
SDA,
ALERT#,
SCLK
Data, alert and clock signal for the SVID communication bus between the CPU and VR1 and VR2.
22
PGOODG Power-good open-drain output indicating when VR2 is able to supply a regulated voltage. Pull-up externally with a 680Ω
resistor to +5V or 1.0kΩ to 3.3V.
23
IMONG Current monitoring output pin for VR2. The current sense signal from ISUMNG and ISUMPG is output on this pin to generate
a voltage proportional to the output current of VR2.
24
VWG A resistor from this pin to COMPG programs the PWM switching frequency for VR1.
25
COMPG This is a dual function pin. This pin is the output of the error amplifier for VR2. A resistor connected from this pin to GND
programs IMAX for VR2 and TMAX for both VR1 and VR2. Refer to Table 8 on page 28.
26
FBG Inverting input of the error amplifier for VR2.
27
RTNG VR2 remote voltage sensing return input. Connect this pin to the remote ground sensing location.
28, 29
ISUMPG, VR2 current sense input pin for current monitoring, droop current and overcurrent detection.
ISUMNG
30
NTCG One of the thermistor network inputs to the thermal monitoring circuit used to control the VR_HOT# signal. Use this pin to
monitor the temperature of VR2. Place the NTC close to the desired thermal detection point on the PCB.
31
VR_HOT# Open drain thermal overload output indicator.
32
PVCCG Input voltage bias for the internal gate driver for VR2. Connect +12V to this pin. Decouple with at least a 1µF MLCC capacitor
and place it as close to the pin as possible.
33
LGATEG Output of the VR2 low-side MOSFET gate driver. Connect this pin to the gate of the VR2 low-side MOSFET.
34
BOOTG Connect a MLCC capacitor from this pin to the PHASEG pin. The boot capacitor is charged through an internal boot diode
connected from the PVCCG pin to the BOOTG pin.
35
UGATEG Output of the VR2 high-side MOSFET gate drive. Connect this pin to the gate of the VR2 high-side MOSFET.
36
PHASEG Current return path for the VR2 high-side MOSFET gate driver. Connect this pin to the node connecting the source of the
high-side MOSFET, the drain of the low-side MOSFET and the output inductor of VR2.
37
PWM4 PWM output for phase 4 of VR1. When PWM4 is pulled to +5V VCC, the controller will disable phase 4 of VR1.
38
PWM3 PWM output for phase 3 of VR1. When PWM3 is pulled to +5V VCC, the controller will disable phase 3 of VR1.
39
PHASE2 Current return path for the VR1 phase 2 high-side MOSFET gate driver. Connect this pin to the node connecting the source of
the high-side MOSFET, the drain of the low-side MOSFET and the output inductor of phase 2.
40
UGATE2 Output of the VR1 phase 2 high-side MOSFET gate drive. Connect this pin to the gate of the high-side MOSFET of phase 2.
3
FN6898.1
September 5, 2013