ISL6363_14 Datasheet, PDF (17/32 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12™ Desktop CPUs

ISL6363
Rdroop
Vdroop
FB
Idroop
VCCSENSE
VR LOCAL VO
“CATCH”
RESISTOR
E/A
COMP
INTERNAL
TO IC
Σ
VID
DAC
VDAC
RTN
X1
VSS
VSSSENSE
“CATCH”
RESISTOR
FIGURE 9. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
I_droop flows through resistor R_droop and creates a voltage drop as
shown in Equation 2.
V_droop = R_droop × I_droop
(EQ. 2)
V_droop is the droop voltage required to implement load line.
Changing R_droop or scaling I_droop can both change the load line
slope. Since I_droop also sets the overcurrent protection level, it is
recommended to first scale I_droop based on OCP requirement,
then select an appropriate R_droop value to obtain the desired
load line slope.
Differential Voltage Sensing
Figure 9 also shows the differential voltage sensing scheme.
VCC_SENSE and VSS_SENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSS_SENSE voltage and add it to the DAC output. The error
amplifier regulates the inverting and the non-inverting input
voltages to be equal as shown in Equation 3:
V
CC_S
E
N
SE
+
V
dr
o
o
p
=
V_DAC + VSS_SENSE
(EQ. 3)
Rewriting Equation 3 and substitution of Equation 2 gives
VCC_SENSE – VSS_SENSE = V_DAC – R_droop × I_droop
(EQ. 4)
Equation 4 is the exact equation required for load line
implementation.
The VCC_SENSE and VSS_SENSE signals come from the processor die.
The feedback will be open circuit in the absence of the processor. As
Figure 9 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage
feedback if the system is powered up without a processor installed.
Phase Current Balancing
The ISL6363 monitors individual phase average current by
monitoring the ISEN1, ISEN2, ISEN3, and ISEN4 voltages.
Figure 10 shows the current balancing circuit recommended for
ISL6363 for a 3-Phase configuration as an example. Each phase
node voltage is averaged by a low-pass filter consisting of R_isen
and C_isen, and presented to the corresponding ISEN pin. R_isen
should be routed to the inductor phase-node pad in order to
eliminate the effect of phase node parasitic PCB DCR.
Equations 5 through 7 give the ISEN pin voltages:
V_ISEN1 = (R_dcr1 + R_pcb1) × I_L1
V_ISEN2 = (R_dcr2 + R_pcb2) × I_L2
V_ISEN3 = (R_dcr3 + R_pcb3) × I_L3
(EQ. 5)
(EQ. 6)
(EQ. 7)
Where R_dcr1, R_dcr2 and R_dcr3 are inductor DCR; R_pcb1, R_pcb2
and R_pcb3 are parasitic PCB DCR between the inductor output
side pad and the output voltage rail; and I_L1, I_L2 and I_L3 are
inductor average currents.
ISEN3
INTERNAL
TO IC
ISEN2
Phase3
Risen
Cisen
Phase2
Risen
Cisen
ISEN1
Phase1
Risen
Cisen
L3
Rdcr3
Rpcb3
IL3
L2
Rdcr2 _Rpcb2
Vo
IL2
L1
Rdcr1 _Rpcb1
IL1
FIGURE 10. CURRENT BALANCING CIRCUIT
The ISL6363 will adjust the phase pulse-width relative to the
other phases to make V_ISEN1 = V_ISEN2 = V_ISEN3, thus, to achieve
I_L1 = I_L2 = I_L3, when there are R_dcr1 = R_dcr2 = R_dcr3 and
R_pcb1 = R_pcb2 = R_pcb3.
Using the same components for L1, L2 and L3 will provide a good
match of R_dcr1, R_dcr2 and R_dcr3. Board layout will determine
R_pcb1, R_pcb2 and R_pcb3. It is recommended to have symmetrical
layout for the power delivery path between each inductor and the
output voltage rail, such that R_pcb1 = R_pcb2 = R_pcb3.
ISEN3
Cisen
V3p
Phase3
Risen
Risen
L3
Rdcr3 _Rpcb3
IL3 _V3n
INTERNAL
TO IC
ISEN2
Cisen
Risen
V2p
Phase2
Risen
Risen
L2
Rdcr2 _{Rpcb2 Vo}
IL2 _V2n
ISEN1
Cisen
Risen
V1p
Phase1
Risen
Risen
L1 Rdcr1
Rpcb1
IL1 _V1n
Risen
FIGURE 11. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
Sometimes it is difficult to implement symmetrical layout. For
the circuit shown in Figure 10, asymmetric layout causes
different R_pcb1, R_pcb2 and R_pcb3, thus current imbalance.
Figure 11 shows a differential-sensing current balancing circuit
recommended for the ISL6363. The current sensing traces
should be routed to the inductor pads so they only pick up the
inductor DCR voltage. Each ISEN pin sees the average voltage of
17
FN6898.1
September 5, 2013