ISL62883C Datasheet, PDF (4/43 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62883C
Functional Pin Descriptions (Continued)
ISL62883C
25
26
27
28
29
30
31 thru 37
38
39
40
pad
SYMBOL
VCCP
LGATE2
VSSP2
PHASE2
UGATE2
BOOT2
VID0 thru
VID6
VR_ON
DPRSLPVR
CLK_EN#
BOTTOM
DESCRIPTION
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at
least 1µF of an MLCC capacitor to VSSP1 and VSSP2 pins respectively.
Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of the
Phase-2 low-side MOSFET.
Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2
pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET.
Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to
the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-2.
Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of the
Phase-2 high-side MOSFET.
Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each
time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
VID input with VID0 = LSB and VID6 = MSB.
Voltage regulator enable input. A high level logic signal on this pin enables the regulator.
Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor
is in deeper sleep mode.
Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore is
within 10% of Vboot.
The bottom pad of ISL62883C is electrically connected to the GND pin inside the IC.It should
also be used as the thermal pad for heat removal.
4
FN7557.1
March 18, 2010