ISL62883C Datasheet, PDF (15/43 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62883C
Start-up Timing
With the controller's V_DD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 1.1V logic high threshold. Figure 10 shows
the typical start-up timing when the ISL62883C is
configured for CPU VR application. The ISL62883C uses
digital soft-start to ramp-up DAC to the boot voltage of
1.1V at about 2.5mV/µs. Once the output voltage is
within 10% of the boot voltage for 13 PWM cycles
(43µs for frequency = 300kHz), CLK_EN# is pulled low
and DAC slews at 5mV/µs to the voltage set by the VID
pins. PGOOD is asserted high in approximately 7ms.
Similar results occur if VR_ON is tied to V_DD, with the
soft-start sequence starting 120µs after V_DD crosses the
POR threshold.
Figure 11 shows the typical start-up timing when the
ISL62883C is configured for GPU VR application. The
ISL62883C uses digital soft start to ramp up DAC to the
voltage set by the VID pins. The slew rate is 5mV/µs
when there is DPRSLPVR = 0, and is doubled when there
is DPRSLPVR = 1. Once the output voltage is within 10%
of the target voltage for 13 PWM cycles (43µs for
frequency = 300kHz), CLK_EN# is pulled low. PGOOD is
asserted high in approximately 7ms. Similar results occur
if VR_ON is tied to V_DD, with the soft-start sequence
starting 120µs after V_DD crosses the POR threshold.
VDD
VR_ON
DAC
5mV/µs
2.5mV/µs
90% ^Vboot
800µs
VID
COMMAND
VOLTAGE
13 SWITCHING
CYCLES
CLK_EN#
PGOOD
~7ms
FIGURE 10. SOFT-START WAVEFORMS FOR CPU VR
APPLICATION
VDD
VR_ON
SLEW
RATE
90%
120µs
VID COMMAND
VOLTAGE
DAC
13 SWITCHING
CYCLES
CLK_EN#
PGOOD
~7ms
FIGURE 11. SOFT-START WAVEFORMS FOR GPU VR
APPLICATION
Voltage Regulation and Load Line
Implementation
After the start sequence, the ISL62883C regulates the
output voltage to the value set by the VID inputs per
Table 1. The ISL62883C will control the no-load output
voltage to an accuracy of ±0.5% over the range of
0.75V to 1.5V. A differential amplifier allows voltage
sensing for precise voltage regulation at the
microprocessor die.
TABLE 1. VID TABLE
V_O
VID6 VID5 VID4 VID3 VID2 VID1 VID0 (V)
0
0
0
0
0
0
0 1.5000
0
0
0
0
0
0
1 1.4875
0
0
0
0
0
1
0 1.4750
0
0
0
0
0
1
1 1.4625
0
0
0
0
1
0
0 1.4500
0
0
0
0
1
0
1 1.4375
0
0
0
0
1
1
0 1.4250
0
0
0
0
1
1
1 1.4125
0
0
0
1
0
0
0 1.4000
0
0
0
1
0
0
1 1.3875
0
0
0
1
0
1
0 1.3750
0
0
0
1
0
1
1 1.3625
0
0
0
1
1
0
0 1.3500
0
0
0
1
1
0
1 1.3375
0
0
0
1
1
1
0 1.3250
0
0
0
1
1
1
1 1.3125
0
0
1
0
0
0
0 1.3000
0
0
1
0
0
0
1 1.2875
0
0
1
0
0
1
0 1.2750
0
0
1
0
0
1
1 1.2625
0
0
1
0
1
0
0 1.2500
0
0
1
0
1
0
1 1.2375
0
0
1
0
1
1
0 1.2250
0
0
1
0
1
1
1 1.2125
0
0
1
1
0
0
0 1.2000
0
0
1
1
0
0
1 1.1875
0
0
1
1
0
1
0 1.1750
0
0
1
1
0
1
1 1.1625
0
0
1
1
1
0
0 1.1500
0
0
1
1
1
0
1 1.1375
0
0
1
1
1
1
0 1.1250
0
0
1
1
1
1
1 1.1125
15
FN7557.1
March 18, 2010