ISL62883C Datasheet, PDF (24/43 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62883C
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the
NTC network and the R_sum resistors form a voltage
divider, V_cn is always a fraction of the inductor DCR
voltage. It is recommended to have a higher ratio of V_cn
to the inductor DCR voltage, so the droop circuit has
higher signal level to work with.
A typical set of parameters that provide good
temperature compensation are: R_sum = 3.65kΩ,
R_p = 11kΩ, R_ntcs = 2.61kΩ and R_ntc = 10kΩ
(ERT-J1VR103J). The NTC network parameters may
need to be fine tuned on actual boards. One can apply
full load DC current and record the output voltage
reading immediately; then record the output voltage
reading again when the board has reached the thermal
steady state. A good NTC network can limit the output
voltage drift to within 2mV. It is recommended to follow
the Intersil evaluation board layout and current-sensing
network parameters to minimize engineering time.
V_Cn(s) also needs to represent real-time I_o(s) for the
controller to achieve good transient response. Transfer
function A_cs(s) has a pole w_sns and a zero w_L. One
needs to match w_L and w_sns so A_cs(s) is unity gain at
all frequencies. By forcing w_L equal to w_sns and solving
for the solution, Equation 24 gives Cn value.
C_n
=
------------------------------^L--------------------------------
-^R----ⁿ---^t--^c---ⁿ----^e---^t---^×------^R--------^s--^N-----^{u------m------}
R_n
t
c
ne
t
+
-^R----^s---^u---^m---
N
×
D
C
R
(EQ. 24)
For example, given N = 3, R_sum = 3.65kΩ, R_p = 11kΩ,
R_ntcs = 2.61kΩ, R_ntc = 10kΩ, DCR = 0.88mΩ and
L = 0.36µH, Equation 24 gives C_n = 0.406µF.
Assuming the compensator design is correct, Figure 18
shows the expected load transient response waveforms
if C_n is correctly selected. When the load current I_core
has a square change, the output voltage V_core also has
a square response.
If C_n value is too large or too small, V_Cn(s) will not
accurately represent real-time I_o(s) and will worsen the
transient response. Figure 19 shows the load transient
response when C_n is too small. V_core will sag excessively
upon load insertion and may create a system failure.
Figure 20 shows the transient response when C_n is too
large. V_core is sluggish in drooping to its final value.
There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU
reliability.
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FIGURE 18. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
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FIGURE 19. LOAD TRANSIENT RESPONSE WHEN C_n
IS TOO SMALL
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FIGURE 20. LOAD TRANSIENT RESPONSE WHEN C_n
IS TOO LARGE
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RING
BACK
FIGURE 21. OUTPUT VOLTAGE RING BACK PROBLEM
24
FN7557.1
March 18, 2010