ISL62883C Datasheet, PDF (31/43 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62883C
TABLE 6. LAYOUT CONSIDERATION (Continued)
PIN NAME
LAYOUT CONSIDERATION
9 ISEN3/FB2 For ISEN3 function, capacitor C7
decouples it to VSUM-, then through
capacitor C20 to GND. Keep the decoupling
path short and minimize the loop
impedance.
For FB2 function, a capacitor connects this
pin to the COMP pin. Put the capacitor in
general proximity of the controller.
10 ISEN2 Capacitor C9 decouples it to VSUM-, then
through capacitor C20 to GND. Keep the
decoupling path short and minimize the
loop impedance.
11 ISEN1 Capacitor C10 decouples it to VSUM-, then
through capacitor C20 to GND. Keep the
decoupling path short and minimize the
loop impedance.
12
VSEN Place the VSEN/RTN filter (C12, C13) in
13
RTN
close proximity of the controller for good
decoupling.
14 ISUM- Place the current sensing circuit in general
15
ISUM+
proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R42 next to phase-1
inductor (L1) so it senses the inductor
temperature correctly.
Each phase of the power stage sends a pair
of VSUM+ and VSUM- signals to the
controller. Run these two signals traces in
parallel fashion with decent width
(>20mil).
IMPORTANT: Sense the inductor current by
routing the sensing circuit to the inductor
pads.
Route R63 and R71 to the phase-1 side
pad of inductor L1. Route R88 to the
output side pad of inductor L1.
Route R65 and R72 to the phase-2 side
pad of inductor L2. Route R90 to the
output side pad of inductor L2.
If possible, route the traces on a different
layer from the inductor pad layer and use
vias to connect the traces to the center of
the pads. If no via is allowed on the pad,
consider routing the traces into the pads
from the inside of the inductor. The
following drawings show the two preferred
ways of routing current sensing traces.
Inductor
Inductor
Vias
Current-Sensing
Traces
Current-Sensing
Traces
16
VDD A capacitor (C16) decouples it to GND.
Place it in close proximity of the controller.
17
VIN A capacitor (C17) decouples it to GND.
Place it in close proximity of the controller.
TABLE 6. LAYOUT CONSIDERATION (Continued)
PIN NAME
LAYOUT CONSIDERATION
18
IMON Place the filter capacitor (C21) close to the
CPU.
19 BOOT1 Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close.
20 UGATE1 Run these two traces in parallel fashion
21
PHASE1
with decent width (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close. Recommend routing
PHASE1 trace to the phase-1 high-side
MOSFET (Q2 and Q8) source pins instead
of general phase-1 node copper.
22 VSSP1 Run these two traces in parallel fashion
23
LGATE1
with decent width (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close. Recommend routing
VSSP1 to the phase-1 low-side MOSFET
(Q3 and Q9) source pins instead of general
power ground plane for better
performance.
24
PWM3 No special consideration.
25
VCCP A capacitor (C22) decouples it to GND.
Place it in close proximity of the controller.
26 LGATE2 Run these two traces in parallel fashion
27
VSSP2
with decent width (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close. Recommend routing
VSSP2 to the phase-2 low-side MOSFET
(Q5 and Q1) source pins instead of general
power ground plane for better
performance.
28 PHASE2 Run these two traces in parallel fashion
29
UGATE2
with decent width (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close. Recommend routing
PHASE2 trace to the phase-2 high-side
MOSFET (Q4 and Q10) source pins instead
of general phase-2 node copper.
30 BOOT2 Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing
over or getting close.
31~3 VID0~6 No special consideration.
7
38 VR_ON No special consideration.
39 DPRSLPVR No special consideration.
40 CLK_EN# No special consideration.
Other
Phase
Node
Minimize phase node copper area. Don’t
let the phase node copper overlap
with/getting close to other sensitive
traces. Cut the power ground plane to
avoid overlapping with phase node copper.
Other
Minimize the loop consisting of input
capacitor, high-side MOSFETs and low-side
MOSFETs (e.g.: C27, C33, Q2, Q8, Q3 and
Q9).
31
FN7557.1
March 18, 2010