ISL62883C Datasheet, PDF (13/43 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

ISL62883C
Theory of Operation
Multiphase R^3™ Modulator
VW
MASTER CLOCK CIRCUIT
MASTER
MASTER ^COMP
CLOCK _Vcrm
CLOCK
Phase
Sequencer
gmVo
Crm
Clock1
Clock2
Clock3
VW
Vcrs1
Crs1
VW
Vcrs2
Crs2
VW
Vcrs3
Crs3
SLAVE CIRCUIT 1
Clock1 S PWM1 ^{Phase1 L1}
Q
R
IL1
gm
SLAVE CIRCUIT 2
Clock2 S PWM2 ^{Phase2 L2}
Q
R
IL2
gm
SLAVE CIRCUIT 3
Clock3 S PWM3 ^{Phase3 L3}
Q
R
IL3
gm
Vo
Co
FIGURE 5. R³â„¢ MODULATOR CIRCUIT
VW
Vcrm
COMP
Master
Clock
Clock1
PWM1
Clock2
PWM2
Clock3
PWM3
VW
Hysteretic
W indow
Vcrs2 Vcrs3 Vcrs1
FIGURE 6. R³â„¢ MODULATOR OPERATION
PRINCIPLES IN STEADY STATE
Vcrm
Master
Clock
Clock1
PWM1
Clock2
PWM2
Clock3
PWM3
VW
COMP
VW
Vcrs1
Vcrs3
Vcrs2
FIGURE 7. R³â„¢ MODULATOROPERATION
PRINCIPLES IN LOAD INSERTION
RESPONSE
The ISL62883C is a multiphase regulators implementing
Intel™ IMVP-6.5™ protocol. It can be programmed for
1-, 2- or 3-phase operation. It uses Intersil patented
R³â„¢ (Robust Ripple Regulator™) modulator. The R³â„¢
modulator combines the best features of fixed
frequency PWM and hysteretic PWM while eliminating
many of their shortcomings. Figure 5 conceptually
shows the ISL62883C multiphase R³â„¢ modulator
circuit, and Figure 6 shows the operation principles.
A current source flows from the VW pin to the COMP
pin, creating a voltage window set by the resistor
between the two pins. This voltage window is called
VW window in the following discussion.
Inside the IC, the modulator uses the master clock
circuit to generate the clocks for the slave circuits. The
modulator discharges the ripple capacitor C_rm with a
current source equal to g_mV_o, where g_m is a gain
factor. C_rm voltage V_crm is a sawtooth waveform
traversing between the VW and COMP voltages. It
resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer
distributes the master clock signal to the slave circuits.
If the ISL62883C is in 3-phase mode, the master clock
signal will be distributed to the three phases, and the
Clock1~3 signals will be 120° out-of-phase. If the
ISL62883C is in 2-phase mode, the master clock signal
will be distributed to Phases 1 and 2, and the Clock1
and Clock2 signals will be 180° out-of-phase. If the
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FN7557.1
March 18, 2010