ISL3874 Datasheet, PDF (4/33 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI

ISL3874
TABLE 1. HOST INTERFACE PINS (Continued)
PIN
PIN NAME NUMBER
PIN I/O TYPE
DESCRIPTION
HBE0
H16 5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE0 applies to byte 0 (HAD7-HAD0).
HINTA
C6 CMOS, Output
PCI Bus Interrupt A
HRESET
D6 5V Tol, CMOS, Input PCI reset.
HFRAME B15 5V Tol, BiDir
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate
that a bus transaction is beginning, and data transfers continue while this signal is asserted. When
FRAME is deasserted, the PCI bus transaction is in the final data phase.
HIRDY
A15 5V Tol, CMOS, BiDir PCI initiator ready. HIRDY indicates the PCI bus initiators ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of PCLK where both HIRDY and
HTRDY are asserted. Until HIRDY and HTRDY are both sampled asserted, wait states are inserted.
HTRDY
A16 5V Tol, CMOS, BiDir PCI target ready. HTRDY indicates the primary bus targets ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of PCLK when both HIRDY
and HTRDY are asserted. Until both HIRDY and HTRDY are asserted, wait states are inserted.
HREQ
B7 CMOS, Output
PCI bus request. HREQ is asserted by the ISL3874 to request access to the PCI bus as an initiator.
HSERR
B16 CMOS, Output
PCI system error. HSERR is an output that is pulsed from the ISL3874 when enabled through the
command register indicating a system error has occurred. The ISL3874 need not be the target of
the PCI cycle to assert this signal. When HSERR is enabled in the control register, this signal also
pulses, indicating that an address parity error has occurred on a CardBus interface.
HSTOP
C16 5V Tol, CMOS, BiDir PCI cycle stop signal. HSTOP is driven by a PCI target to request the initiator to stop the current
PCI bus transaction. HSTOP is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
HDEVSEL D15 5V Tol, CMOS, BiDir PCI device select. The ISL3874 asserts HDEVSEL to claim a PCI cycle as the target device. As a
PCI initiator on the bus, the ISL3874 monitors HDEVSEL until a target responds. If no target
responds before timeout occurs, the ISL3874 terminates the cycle with an initiator abort.
HPERR
D16 5V Tol, CMOS, BiDir PCI bus parity. In all PCI bus read and write cycles, the ISL3874 calculates even parity across the
HD31-HAD0 and BE3-BE0 buses. As an initiator during PCI cycles, the ISL3874 outputs this parity
indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared
to the initiator parity indicator. A compare error results in the assertion of a parity error (PERR).
HGNT
C7 5V Tol, CMOS, ST PCI bus grant. HGNT is driven by the PCI bus arbiter to grant the ISL3874 access to the PCI bus
Input
after the current data transaction has completed. HGNT may or may not follow a PCI bus request,
depending on the PCI bus parking algorithm.
HPCLK
A7 5V Tol, CMOS,
Input
HPCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
HPAR
B13 5V Tol, CMOS, BiDir PCI bus parity.
HIDSEL
C11 5V Tol, CMOS,
Input
Initialization device select. HIDSEL selects the ISL3874 during configuration space accesses.
HIDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
HPME
B8 CMOS, Output
Power Management Event Output. HPME provides output for PME signals.
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