ISL3874 Datasheet, PDF (22/33 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI

ISL3874
In the short preamble mode, the modem uses a
synchronization field of 56 zero symbols along with an SFD
transmitted at 1Mbps. The short header is transmitted at
2Mbps. The synchronization preamble is all 0’s to distinguish
it from the long header mode and the short preamble SFD is
the time reverse of the long preamble SFD. The duration of
the short preamble and header is 96µs.
Start Frame Delimiter (SFD) Field (16 Bits) - This field is
used to establish the link frame timing. The ISL3874 will not
declare a valid data packet, even if it PN acquires, unless it
detects the SFD. The ISL3874 receiver auto-detects if the
packet is long or short preamble and sets SFD time-out. The
timer starts counting after initialization of the de-scrambler is
complete.
The four fields for the header shown in Figure 13 are:
Signal Field (8 Bits) - This field indicates what data rate the
data packet that follows the header will be. The ISL3874
receiver looks at the signal field to determine whether it
needs to switch from DBPSK demodulation into DQPSK, or
CCK demodulation at the end of the preamble and header
fields.
Service Field (8 Bits) - The MSB of this field is used to
indicate the correct length when the length field value is
ambiguous at 11Mbps. See IEEE STD 802.11 for definition
of the other bits. Bit 2 is used by the ISL3874 to indicate that
the carrier reference and the bit timing references are
derived from the same oscillator (locked oscillators).
Length Field (16 Bits) - This field indicates the number of
microseconds it will take to transmit the payload data
(PSDU). The external controller (MAC) will check the length
field in determining when it needs to de-assert RX_PE.
CCITT - CRC 16 Field (16 Bits) - This field includes the
16-bit CCITT - CRC 16 calculation of the three header fields.
This value is compared with the CCITT - CRC 16 code
calculated at the receiver. The ISL3874 receiver will indicate
a CCITT - CRC 16 error via CR24 bit 2 and will lower
MD_RDY and reset the receiver to the acquisition mode if
there is an error.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (frame check sequence). It is the ones complement of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x¹⁶ + x¹² + x⁵ + 1
The protected bits are processed in transmit order. All CRC
calculations are made ahead of data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected fields are shifted through
the register. The output is then complemented and the
residual shifted out MSB first.
The following Configuration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
CR3 - Defines the short preamble length minus the SFD in
symbols. The 802.11 protocol requires a setting of 56d = 38h
for the optional short preamble.
CR4 - Defines the long preamble length minus the SFD in
symbols. The 802.11 protocol requires a setting of
128d = 80h for the mandatory long preamble.
CR5 Bits 0, 1 - These bits of the register set the Signal field
to indicate what modulation is to be used for the data portion
of the packet.
CR6 - The value to be used in the Service field.
CR7 and CR8 - Defines the value of the transmit data length
field. This value includes all symbols following the last
header field symbol and is in microseconds required to
transmit the data at the chosen data rate.
The packet consists of the preamble, header and MAC
Protocol Data Unit (MPDU). The data is transmitted exactly
as received from the control processor. Some dummy bits
are appended to the end of the packet to ensure an orderly
shutdown of the transmitter. This prevents spectrum
splatter. At the end of a packet, the MAC shuts the
transmitter down.
Scrambler and Data Encoder Description
The modulator has a data scrambler that implements the
scrambling algorithm specified in the IEEE 802.11 standard.
This scrambler is used for the preamble, header, and data in
all modes. The data scrambler is a self synchronizing circuit.
It consists of a 7-bit shift register with feedback from
specified taps of the register. Both transmitter and receiver
use the same scrambling algorithm. The scrambler can be
disabled by setting CR32 bit 2 to 1.
NOTE: Be advised that the IEEE 802.11 compliant scrambler in the
ISL3874 has the property that it can lock up (stop scrambling) on
random data followed by repetitive bit patterns. The probability of this
happening is 1/128. The patterns that have been identified are all
zeros, all ones, repeated 10s, repeated 1100s, and repeated
111000s. Any break in the repetitive pattern will restart the
scrambler. To ensure that this does not cause any problem, the CCK
waveform uses a ping pong differential coding scheme that breaks
up repetitive 0’s patterns.
PREAMBLE (SYNC) SFD
128/56 BITS
16 BITS
PREAMBLE
SIGNAL FIELD SERVICE FIELD LENGTH FIELD CRC16
8 BITS
8 BITS
16 BITS
16 BITS
HEADER
FIGURE 13. 802.11 PREAMBLE/HEADER
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