ISL3874 Datasheet, PDF (14/33 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI

ISL3874
MWEL/MWE is the only write control, and MOE is the read
output enable.
For 16-bit spaces constructed from 8-bit memories, the
ISL3874 dynamically configures pin MA0/MWEH cycle-by-
cycle as the high byte write enable, MWEL as the low write
enable signal, and MOE as the read output enable.
For 16-bit spaces constructed from single-chip x16
memories (such as SRAMs), the ISL3874 dynamically
configures pin MA0/MWEH cycle-by-cycle as the upper byte
enable. Pin MLBE is connected as the low byte enable,
MWEL/MWE is the write control, and MOE is the read output
enable.
These memory implementations require no external logic.
The memory spaces may each be constructed from any type
of memory desired. The only restriction is that a single
memory space must be constructed from the same type of
memory; for example, data space may not use both x8 and
x16 memories, it must be all x8, or all x16. This restriction
does not apply across memory spaces; e.g., code space
may use a x8 memory and data space a single x16 memory,
or code space two x8 memories and data space a single x8
memory.
Serial EEPROM Memory Interface
The ISL3874 contains a small on-ship ROM firmware which
was added to allow the CIS or CIS plus firmware image to be
transferred from a off-chip serial nonvolatile memory device
to RAM after a system reset. This allows a system
configuration without a parallel Flash device. The operating
frequency for the 24C08 Serial EEPROM must be 400kHz
with an operating voltage of 3.3V. Refer to Figure 8 for
additional details on configuring the serial memory to the
ISL3874.
The Power On Reset Configuration Section in this document
provides additional details on memory selection and control
after a reset condition.
PC Card Interface
The PCI Host Interface allows access to the ISL3874
memory and host registers using PCI memory read or write
transactions.
The host interface supports Target Mode operation
transferring double words. Direct memory access to the
ISL3874 memory space using Aux port transfers is
supported in Target Mode. BAP transfers operate in Target
Mode in a similar manner to how they worked on the
HFA3842 and thus allow quick porting of base functionality
HFA3842 driver code to this part.
Most of the host side registers have been preserved except
where functionality is no longer needed. For example, the
attribute FCR registers are not implemented since attribute
space does not exist for the PCI interface. Only memory
space is implemented in this part so PCI I/O read or write
operations are not defined.
PCI Interface Configuration
The PCI core has two sets of configuration registers. One
set is read-only and configured to default values or set up by
ISL3874 firmware on reset. This set is used by the host to
determine what type of card this is, and what drivers need to
be loaded. The other set is the host configuration registers.
These are written by the host to configure various options
and responses of the PCI card.
During reset the core’s strapping options cause one of two
scenarios to occur for loading the read-only PCI
configuration registers. If the part is set to power up and run
then the ISL3874 firmware is responsible for fetching values
from its memory space and loading them into the proper
registers. Note that the interface will be unable to respond to
host commands including configuration commands until
these registers have been loaded.
If the part is set to power up and go idle then default values
are loaded into the read-only registers so that the PCI
interface can be initialized by the host. This mode is most
likely the case when downloading firmware code via the Aux
port. Since there is no existing firmware to control the part
the default values allow the host to configure the rest of the
interface enough to be able to download code into the
memory space of the ISL3874.
The read-only registers set the device id, vendor id, class
code, revision id, header type, subsystem id, subsystem
vendor id, maximum latency, minimum grant, and the
interrupt pin. These registers are all 16 bits wide and are
loaded by the DBus. They must be loaded in the following
order: {max_lat, min_gnt}, {class_code[23:16], header},
class_code[15:0], {int_pin, rev_id}, subsys_id,
subsys_vendor_id, device_id, vendor_id.
The default values are:
• device_id 0x3873
• vendor_id 0x1260 // Intersil PCI SIG vendor id.
• class_code 0x02_8000
• subsys_id 0x0000
• subsys_vendor_id 0x1260 // Intersil PCI SIG vendor id.
• rev_id 0x01
• header 0x00
• max_lat 0x00
• min_gnt 0x00
• int_pin 0x01 // Int A
On reset or power up the PCI interface has several host
configuration registers that must be written by the host
before normal target memory read/write transactions can be
used. Target operations are enabled once the Memory Base
Address and the Command registers have been written.
14