ISL3874 Datasheet, PDF (28/33 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI

ISL3874
to 2 bits. In the CCK mode, when a symbol decision error is
made, up to 6 bits may be in error although on average only 3
bits will be in error. Secondly, when the bits are processed by
the descrambler, these errors are further extended. The
descrambler is a 7-bit shift register with two taps exclusive or’ed
with the bit stream. Thus, each error is extended by a factor of
three. Multiple errors can be spaced the same as the tap
spacing, so they can be canceled in the descrambler. In this
case, two wrongs do make a right. Given all that, if a single
error is made the whole packet is discarded anyway, so the
error extension property has no effect on the packet error rate.
It should be taken into account if a forward error correction
scheme is contemplated.
Descrambling is self synchronizing and is done by a
polynomial division using a prescribed polynomial. A shift
register holds the last quotient and the output is the exclusive-
or of the data and the sum of taps in the shift register.
I_REF
V_REF
TX_AGC_IN
TX_IF_AGC
ANTSEL
ANTSEL
V_DD (ANALOG)
GND (ANALOG)
V_DD (DIGITAL)
GND (DIGITAL)
6-BIT
ADC
6-BIT
DAC
TX AGC
CONTROL
REGISTER
TRANSMIT
FILTER
PREAMBLE/HEADER
CRC-16
GENERATOR
TIMING
GENERATOR
MCLK
MODULATOR,
BARKER/CCK
TX_DATA
SCRAMBLER
TX
STATE
CONTROL
TXI
DAC
DAC
TXQ
TX_RDY
TXCLK
TXD
MAC
CONTROL
SIGNALS
TX_PE
BBP_CLK
FIGURE 16. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
SAMPLES
AT 2X CHIP
RATE
CORRELATION
PEAK
CORRELATION TIME
T0
CORRELATOR OUTPUT IS THE RESULT OF CORRELATING
THE PN SEQUENCE WITH THE RECEIVED SIGNAL
T0 + 1 SYMBOL CORRELATOR
OUTPUT REPEATS
FIGURE 17. CORRELATION PROCESS
EARLY
ON-TIME
LATE
T0 + 2 SYMBOLS
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