ISL3874 Datasheet, PDF (20/33 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI

ISL3874
TABLE 14. I, Q, A/D SPECIFICATIONS
PARAMETER
MIN
TYP
Full Scale Input Voltage (V_P-P)
Input Bandwidth (-0.5dB)
0.90
1.00
-
11MHz
Input Capacitance (pF)
-
2
Input Impedance (DC)
5kΩ
-
f_S (Sampling Frequency)
-
22MHz
MAX
1.10
-
-
-
-
AGC Circuit
The AGC circuit as shown in Figure 11 is designed to adjust
for signal level variations and optimize A/D performance for
the I and Q inputs by maintaining the proper headroom on
the 6-bit converters. There are two gain stages being
controlled. At RF, the gain control is a 30dB step change.
This RF gain control optimizes the receiver dynamic range
when the signal level is high and maintains the noise figure
of the receiver when it is needed most at low signal level. At
IF, the gain control is linear and covers the bulk of the gain
control range of the receiver.
The AGC loop is partially digital which allows for holding the
gain fixed during a packet. The AGC sensing mechanism uses
a combination of the I and Q A/D converters and the detected
signal level in the IF to determine the gain settings. The A/D
outputs are monitored in the ISL3874 for the desired nominal
level. When it is reached, by adjusting the receiver gain, the
gain control is locked for the remainder of the packet.
RX_AGC_IN Interface
The signal level in the IF stage is monitored to determine
when to impose the 30dB gain reduction in the RF stage.
This maximizes the dynamic range of the receiver by
keeping the RF stages out of saturation at high signal levels.
When the IF circuits’ sensor output reaches 0.5V_DD, the
ISL3874 comparator switches in the 30dB pad and also
adds 30dB of gain to the IF AGC amplifier. This
compensates the IF AGC and RSSI measures.
TX I/Q DAC Interface
The transmit section outputs balanced differential analog
signals from the transmit DACs to the HFA3783. These are
DC coupled and digitally filtered.
Test Port
The ISL3874 provides the capability to access a number of
internal signals and/or data through the Test port, pins TEST
7:0. The test port is programmable through configuration
register (CR34). Any signal on the test port can also be read
from configuration register (CR50) via the serial control port.
Additionally, the transmit DACs can be configured to show
signals in the receiver via CR14. This allows visibility to
analog like signals that would normally be very difficult to
capture.
Transmitter Description
The ISL3874 transmitter is designed as a Direct Sequence
Spread Spectrum Phase Shift Keying (DSSS PSK) modulator.
It can handle data rates of up to 11Mbps (refer to AC and DC
specifications). The various modes of the modulator are
Differential Binary Phase Shift Keying (DBPSK) for 1Mbps,
Differential Quaternary Phase Shift Keying (DQPSK) for
2Mbps, and Complementary Code Keying (CCK) for 5.5Mbps
and 11Mbps. These implement data rates as shown in Table
15. The major functional blocks of the transmitter include a
network processor interface, DPSK modulator, high rate
modulator, a data scrambler and a spreader, as shown in
Figure 16. CCK is essentially a quadraphase form of M-ARY
Orthogonal Keying. A description of that modulation can be
found in Chapter 5 of: “Telecommunications System
Engineering”, by Lindsey and Simon, Prentis Hall publishing.
TThe preamble is always transmitted as the DBPSK waveform
while the header can be configured to be either DBPSK, or
DQPSK, and data packets can be configured for DBPSK,
DQPSK, or CCK. The preamble is used by the receiver to
achieve initial PN synchronization while the header includes the
necessary data fields of the communications protocol to
establish the physical layer link. The transmitter generates the
synchronization preamble and header and makes the DBPSK
to DQPSK or CCK switchover, as required.
HFA368X
RX_RF_AGC
RX_IF_DET
RX_IF_AGC
HFA3783
RX_I±
RX_Q±
1
THRESH. ₁
DETECT
7
IF
DAC
6
I ADC
6
Q ADC
ISL3874
FIGURE 11. AGC CIRCUIT
AGC
CTL
DEMOD
I/O
DATA I/O
20