ISL3874 Datasheet, PDF (27/33 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI

ISL3874
consecutive SQ1s will cause the part to finish the acquisition
phase and enter the tracking phase.
Prior to initial acquisition the NCO is inactive (0Hz) and
carrier phase measurement are done on a symbol by symbol
basis. After acquisition, coherent DPSK demodulation is in
effect. After a brief setup time as illustrated on the timeline,
the signal begins to emerge from the demodulator.
It takes 7 more symbols to seed the descrambler before valid
data is available. This occurs in time for the SFD to be received.
At this time the demodulator is tracking and in the coherent
PSK demodulation mode so it will no longer acquire new
signals. If a much larger signal overrides the signal being
demodulated (a collision), the demodulator will abort the
tracking process and attempt to acquire the new signal. Failure
to find an SFD within the SFD timeout interval will result in a
receiver reset and return to acquisition mode.
Channel Matched Filter (CMF) Description
The receive section shown in Figure 18 operates on the
RAKE receiver principle which maximizes the SNR of the
signal by combining the energy of multipath signal
components. The RAKE receiver is implemented with a
Channel Matched Filter (CMF) using a FIR filter structure with
16 taps. The CMF is programmed by calculating the Channel
Impulse Response (CIR) of the channel and mathematically
manipulating that to form the tap coefficients of the CMF.
Thus, the CMF is set to compensate the channel
characteristics that distort the signal. Since the calculation of
the CIR is inaccurate at low SNR or in the presence of strong
CW interference, the chip has thresholds (CR36 to CR39) that
are set to substitute a default CMF shape under those
conditions. This default CMF shape is designed to
compensate only the known transmit and receive non
linearity.
PN Correlators Description
There are two types of correlators in the ISL3874 baseband
processor. The first is a parallel matched filter correlator that
correlates for the Barker sequence used in preamble, header,
and PSK data modes. This Barker code correlator is designed
to handle BPSK spreading with carrier offsets up to ±50ppm
and 11 chips per symbol. Since the spreading is BPSK, the
correlator is implemented with two real correlators, one for the
I and one for the Q Channel. The same Barker sequence is
always used for both I and Q correlators.
These correlators are time invariant matched filters otherwise
known as parallel correlators. They use one sample per chip
for correlation although two samples per chip are processed.
The correlator despreads the samples from the chip rate back
to the original symbol rate giving 10.4dB processing gain for
11 chips per symbol. While despreading the desired signal,
the correlator spreads the energy of any non correlating
interfering signal.
The second form of correlator is the parallel correlator bank
used for detection of the CCK modulation. For the CCK modes,
the 64 wide bank of parallel correlators is implemented with a
Fast Walsh Transform to correlate the 4 or 64 code
possibilities. This greatly simplifies the circuitry of the
correlation function. It is followed by a biggest picker which
finds the biggest of 4 or 64 correlator outputs depending on the
rate. This is translated into 2 or 6 data bits. The detected output
is then processed through the differential phase decoder to
demodulate the last two bits of the symbol.
Data Demodulation and Tracking
Description (DBPSK and DQPSK Modes)
The signal is demodulated from the correlation peaks tracked
by the symbol timing loop (bit sync) as shown in Figure 18. The
frequency and phase of the signal is corrected using the NCO
that is driven by the phase locked loop. Averaging the phase
errors over 10 symbols gives the necessary frequency
information for seeding the NCO operation.
Data Decoder and Descrambler
Description
The data decoder that implements the desired DQPSK
coding/decoding as shown in Table 20. The data is formed
into pairs of bits called dibits. The left bit of the pair is the first
in time. This coding scheme results from differential coding
of the dibits. Vector rotation is counterclockwise for a
positive phase shift, but can be reversed with bit 7 or 6 of
CR1.
For DBPSK, the decoding is simple differential decoding.
TABLE 20. DQPSK DATA DECODER
PHASE SHIFT
DIBIT PATTERN (D0, D1)
D0 IS FIRST IN TIME
0
00
+90
01
+180
11
-90
10
The data scrambler and de-scrambler are self synchronizing
circuits. They consist of a 7-bit shift register with feedback of
some of the taps of the register. The scrambler is designed
to ensure smearing of the discrete spectrum lines produced
by the PN code.
One thing to keep in mind is that both the differential decoding
and the descrambling cause error extension or burst errors.
This is due to two properties of the processing. First, the
differential decoding process causes errors to occur on pairs of
symbols. When a symbol’s phase is in error, the next symbol
will also be decoded wrong since the data is encoded in the
change in phase from one symbol to the next. Thus, two errors
are made on two successive symbols. Therefore up to 4 bits
may be wrong although on the average only 2 are. In QPSK
mode, these may occur next to one another or separated by up
27