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ISL3874 Datasheet, PDF (10/33 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
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ISL3874
AC Electrical Specifications (Continued)
SYNTHESIZER
PARAMETER
SYNTHCLK(PK1) Period
SYNTHCLK(PK1) Width Hi
SYNTHCLK(PK1) Width Lo
SYNTHDATA(PK2) Hold Time from Falling Edge of SYNTHCLK(PK1)
SYNTHCLK(PK1) Falling Edge to SYNLE Inactive
SYSTEM INTERFACE - PCI TIMING
Cycle Time, HPCLK
Pulse Duration, HPCLK High
Pulse Duration, HPCLK Low
Slew Rate, HPCLK
Propagation Delay Time, HPCLK to Signal Valid Delay Time
Propogation Delay Time, HPCLK to Signal Invalid Delay Time
Enable Time, High Impedance to Active Delay Time from HPCLK
Disable Time, Active to High Impedance Delay Time from HPCLK
Setup Time Before HPCLK Valid
Hold Time After HPCLK High
BASEBAND SIGNALS
Full Scale Input Voltage (VP-P)
Input Bandwidth (-0.5dB)
Input Capacitance
Input Impedance (DC)
FS (Sampling Frequency)
Waveforms
ADDRESS
MA(17..1)
RAMCS
MOE
tS2
MD(15..0)
tS1
tE1
SYMBOL
MIN
TYP
MAX
UNITS
tCYC
tH1
tL1
tD2
tD3
tCYC
tH
tL
tS
tV
tINV
tEN
tDIS
tS
tH
90
tCYC/2 - 10
tCYC/2 - 10
0
35
30
11
11
1
-
2
2
-
7
0
0.25
-
-
5
-
-
4,000
ns
-
tCYC/2 + 10 ns
-
tCYC/2 + 10 ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
4
V/ns
-
11
ns
-
-
ns
-
-
ns
-
28
ns
-
-
ns
-
-
ns
0.50
1.0
V
20
-
MHz
5
-
pF
-
-
kΩ
-
22
MHz
tH1
tH2
tD1
FIGURE 1. MAC EXTERNAL MEMORY READ TIMING
10
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