ISL3874 Datasheet, PDF (16/33 Pages) Intersil Corporation – Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI

ISL3874
be connected to one of the upper 24 PCI address lines on
the PCI bus.
HRESET - PCI Card reset signal. This reset signal only
resets the PCI core.
HFRAME - PCI Card FRAME cycle signal. FRAME is driven
by the initiator of a bus cycle. FRAME is asserted to indicate
that a bus transaction is beginning, and data transfers
continue while this signal is asserted. When FRAME is
deasserted, the PCI bus transaction is in the final data
phase.
HIRDY - PCI initiator ready. HIRDY indicates the PCI bus
initiators ability to complete the current data phase of the
transaction. A data phase is completed on a rising edge of
PCLK where both HIRDY and HTRDY are asserted. Until
HIRDY and HTRDY are both sampled asserted, wait states
are inserted.
HPAR - PCI bus parity. The ISL3874 calculates even parity
across the buses HAD(31-0) and HBE(3-0).
HTRDY - PCI target ready. HTRDY indicates the primary bus
targets ability to complete the current data phase of the
transaction. A data phase is completed on a rising edge of
PCLK when both HIRDY and HTRDY are asserted. Until both
HIRDY and HTRDY are asserted, wait states are inserted.
HDEVSEL - PCI device select. The ISL3874 asserts
HDEVSEL to claim a PCI cycle as the target device. As a
PCI initiator on the bus, the ISL3874 monitors HDEVSEL
until a target responds. If no target responds before a
timeout occurs, the ISL3874 terminates the cycle with an
initiator abort.
HSTOP - PCI cycle stop signal. HSTOP is driven by a PCI
target to request the initiator to stop the current PCI bus
transaction. HSTOP is used for target disconnects and is
commonly asserted by target devices that do not support
burst data transfers.
HPERR - PCI parity error indicator. HPERR is driven by a
PCI device to indicate that the calculated parity does not
match HPAR when HPERR is enabled.
HSERR - PCI system error. HSERR is an output that is
pulsed from the ISL3874 when enabled through the
command register indicating a system error has occurred.
The ISL3874 need not be the target of the PCI cycle to
assert this signal. When HSERR is enabled in the control
register, this signal also pulses, indicating that an address
parity error has occurred on a CardBus interface.
HREQ - PCI bus request. HREQ is asserted by the ISL3874
to request access to the PCI bus as an initiator.
HGNT - PCI bus grant. HGNT is driven by the PCI bus
arbiter to grant the ISL3874 access to the PCI bus after the
current data transaction has completed. HGNT may or may
not follow a PCI bus request, depending on the PCI bus
parking algorithm.
HPCLK - HPCLK provides timing for all transactions on the
PCI bus. All PCI signals are sampled at the rising edge of
PCLK.
HPME - Power Management Event Output. HPME provides
output for PME signals.
Register Interface
The logical view of the ISL3874 from the host is a block of 32
word wide registers. These appear in IO space starting at
the base address determined by the socket controller. There
are three types of registers.
HARDWARE REGISTERS (HW)
• 1 to 1 correspondence between addresses and registers.
• No memory arbitration delay, data transfer directly to/from
registers.
• AUX base and offset are write-only, to set up access
through AUX data port.
• Note: All register cycles, including hardware registers,
incur a short wait state on the PC Card bus to insure the
host cycle is synchronized with the ISL3874’s internal
MCLK.
MEMORY MAPPED REGISTERS IN DATA RAM (MM)
• 1 to 1 correspondence.
• Requires memory arbitration, since registers are actually
locations in ISL3874 memory.
• Attribute memory access is mapped into RAM as Base-
address + 0x400.
• AUX port provides host access to any location in ISL3874
RAM (reserved).
BUFFER ACCESS PATH (BAP)
• No 1 to 1 correspondence between register address and
memory address (due to indirect access through buffer
address pointer registers).
• Auto increment of pointer registers after each access.
• Require memory arbitration since buffers are located in
ISL3874 memory.
• Buffer access may incur additional delay for Hardware
Buffer Chaining.
Buffer Access Paths
The ISL3874 has two independent buffer access paths,
which permits concurrent read and write transfers. The
firmware provides dynamic memory allocation between
Transmit and Receive, allowing efficient memory utilization.
On-the-fly allocation of (128-byte) memory blocks as needed
for reception wastes minimal space when receiving
fragments. The ISL3874 hides management of free memory
from the driver, and allows fast response and minimum data
copying for low latency. The firmware provides direct access
to TX and RX buffers based on Frame ID (FID). This
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