ISL6333 Datasheet, PDF (36/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔV_MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
as shown in Equation 42.
ΔV
≈
ESL
⋅
-d---i
dt
+
ESR
⋅
ΔI
(EQ. 42)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of the
output-voltage ripple. As the bulk capacitors sink and source
the inductor AC ripple current (see “Interleaving” on page 17
and Equation 2), a voltage develops across the bulk capacitor
ESR equal to I_C(P-P)(ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage, V_P-
P(MAX)^{, determines the lower limit on the inductance.}
L
≥ ESR ⋅
⎛
⎝
V_IN
–
N
⋅
V_O
U
⎞
T_⎠
⋅
V_OUT
--------f--_S-----_â‹---V----_I--_N-----_â‹---V----_P----_---_P---₍--_M-----_A----_X----₎-------
(EQ. 43)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV_MAX. This places an upper limit on inductance.
Equation 44 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 45
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
L ≤ ^2-----â‹---N------^â‹---C------^â‹---V----^O--- ⋅
(ΔI)²
ΔV_MAX – (ΔI ⋅ ESR)
(EQ. 44)
L
≤
-1---.--2---5-----^â‹---N------^â‹---C--
(ΔI)²
⋅
ΔV_MAX – (ΔI ⋅ ESR)
⋅ _⎝⎛V_IN – V_{O⎠⎞}
(EQ. 45)
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in the “MOSFETs General Design Guide” on
page 31 and they establish the upper limit for the switching
frequency. The lower limit is established by the requirement
for fast transient response and small output-voltage ripple.
Choose the lowest switching frequency that allows the
regulator to meet the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, R_T. Figure 26 and Equation 46
are provided to assist in selecting the correct value for R_T.
500
100
10
50k
100k
1M
2M
SWITCHING FREQUENCY (Hz)
FIGURE 26. R_T vs SWITCHING FREQUENCY
RT
=
[10.61
10
–
( 1.035
⋅
log ( fS ) ) ]
(EQ. 46)
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient
36
FN6520.3
October 8, 2010