ISL6333 Datasheet, PDF (25/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
In Equation 10, V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_OUT is the total output current of
the converter, R_ISEN is the internal sense resistor connected
to the ISEN+ pin, R_FB is the feedback resistor, N is the active
number of channels, and DCR is the Inductor DCR value.
Therefore the equivalent loadline impedance, i.e. droop
impedance, is equal to Equation 11:
R_LL
=
--R----^F----^B--
N
⋅
-D-----C-----R---
R_SET
⋅
4_----0_---0_--
3
(EQ. 11)
Output-Voltage Offset Programming
The controllers allow the designer to accurately adjust the
offset voltage by connecting a resistor, R_OFS, from the OFS
pin to VCC or GND. When R_OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I_OFS) to flow into the OFS pin
and out of the FB pin, providing a negative offset. If R_OFS is
connected to ground, the voltage across it is regulated to
0.3V, and I_OFS flows into the FB pin and out of the OFS pin,
providing a positive offset. The offset current flowing through
the resistor between VSEN and FB will generate the desired
offset voltage which is equal to the product (I_OFS x R_FB).
These functions are shown in Figures 8 and 9.
VDIFF
+
V_OFS
-
R_FB
FB
I_OFS
ISL6333 INTERNAL CIRCUIT
VREF
E/A
R_OFS
OFS
+
0.3V
-
-
1.6V
+
GND
GND
VCC
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Once the desired output offset voltage has been determined,
use Equations 12 and 13 to set R_OFS:
For Negative Offset (connect R_OFS to VCC):
R_OFS
=
--¹---^.--⁶-----^â‹---^R----^F----^B---
V_OFFSET
(EQ. 12)
For Positive Offset (connect R_OFS to GND):
R_OFS
=
--⁰---^.--³-----^â‹---^R----^F----^B---
V_OFFSET
(EQ. 13)
VDIFF
-
V_OFS
+
R_FB
FB
I_OFS
ISL6333 INTERNAL CIRCUIT
VREF
E/A
VCC
R_OFS
OFS
+
0.3V
-
-
1.6V
+
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the controllers
to do this by making changes to the VID inputs. The
controllers are required to monitor the DAC inputs and
respond to on-the-fly VID changes in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption.
The controllers check for VID changes by comparing the
internal DAC code to the VID pin inputs on the positive edge
of an internal 5.55MHz clock. If a new code is established on
the VID inputs and it remains stable for 3 consecutive
readings (360ns to 540ns), the controllers recognize the new
code and begins incrementing/decrementing the DAC in
6.25mV steps at a stepping frequency of 1.85MHz. This
controlled slew rate of 6.25mV/540ns (11.6mV/µs) continues
until the VID input and DAC are equal. Thus, the total time
required for a VID change, t_DVID, is dependent only on the size
of the VID change (ΔV_VID).
The time required for a ISL6333-based converter to make a
1.6V to 0.5V reference voltage change is about 95µs, as
calculated using Equation 14.
t_DVID
=
540
⋅
10^–9
⋅
⎛
⎝
0^---Δ-.^--0V^---0^--V-6^--I--2^D---5^{--⎠⎞}
(EQ. 14)
VID “Off” DAC Codes
The Intel VR11 VID tables include “Off” DAC codes, which
indicate to the controllers to disable all regulation. Recognition
of these codes is slightly different in that they must be stable for
4 consecutive readings of a 5.55MHz clock (540ns to 720ns)
to be recognized. Once an “Off” code is recognized the
controllers latch off, and must be reset by toggling the EN pin.
25
FN6520.3
October 8, 2010