ISL6333 Datasheet, PDF (28/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
Upper MOSFET Gate Drive Voltage Versatility
The controllers provide the user flexibility in choosing the
upper MOSFET gate drive voltage for efficiency
optimization. The controllers tie all the upper gate drive rails
together to the PUVCC pin. Simply applying a voltage from
+5V up to +12V on PUVCC sets all of the upper gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC1, PVCC2_3, PUVCC, BYP1 and VID pins. When
the conditions are met, the controllers begin soft-start. Once
the output voltage is within the proper window of operation,
the controllers assert VR_RDY.
ISL6333 INTERNAL CIRCUIT
VCC
PVCC1
PVCC2_3
PUVCC
BYP1
POR
CIRCUIT
ENABLE
COMPARATOR
EN
+
-
SOFT-START
AND
FAULT LOGIC
0.86V
FIGURE 15. POWER SEQUENCING USING
THRESHOLD-SENSITIVE ENABLE (EN)
FUNCTION
Enable and Disable
While in shutdown mode, the LGATE and UGATE signals
are held low to assure the MOSFETs remain off. The
following input conditions must be met before the controllers
are released from shutdown mode to begin the soft-start
startup sequence:
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the controllers are guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the controllers will not inadvertently turn off unless the
bias voltage drops substantially (see “Electrical
Specifications” on page 13).
2. The voltage on EN must be above 0.86V. The enable
comparator holds the controllers in shutdown until the
voltage at EN rises above 0.86V. The enable comparator
has 104mV of hysteresis to prevent bounce.
3. The driver bias voltage applied at the PVCC1, PVCC2_3,
PVCC2, PVCC3, PUVCC, and BYP1 pins must reach the
internal power-on reset (POR) rising threshold.
Hysteresis between the rising and falling thresholds
assure that once enabled, the controllers will not
inadvertently turn off unless the bias voltages drops
substantially (see “Electrical Specifications” on page 13).
Once all of these conditions are met the controllers will begin
the soft-start sequence and will ramp the output voltage up
as described in “Soft-Start” on page 28.
Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence is composed of four
periods, as shown in Figure 16. Once the controllers are
released from shutdown and soft-start begins (as described
in “Enable and Disable” on page 28), there will be a fixed
delay period, t_d1, of typically 1.10ms. After this delay period,
the controllers will begin the first soft-start ramp, increasing
the output voltage until it reaches the 1.1V VBOOT voltage.
V_OUT, 500mV/DIV
t_d1
t_d2
EN
t_d3 t_d4 t_d5
VR_RDY
500µs/DIV
FIGURE 16. SOFT-START WAVEFORMS
The controllers will then regulate the output voltage at 1.1V
for another fixed delay period, t_d3, of typically 93µs. At the
end of the t_d3 period, the controllers will read the VID
signals. It is recommended that the VID codes be set no
later then 50µs into period t_d3. If the VID code is valid, the
controllers will initiate the second soft-start ramp, regulating
the output voltage up to the VID voltage ± any offset or droop
voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 19.
t_SS = t_d1 + t_d2 + t_d3 + t_d4
(EQ. 19)
During t_d2 and t_d4, the controllers digitally control the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator, which
is defined by the resistor R_SS on the SS pin. The soft-start
28
FN6520.3
October 8, 2010