ISL6333 Datasheet, PDF (18/40 Pages) Intersil Corporation – Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications

ISL6333, ISL6333A, ISL6333B, ISL6333C
.
I_L1 + I_L2 + I_L3, 7A/DIV
I_L3, 7A/DIV
PWM3, 5V/DIV
I_L2, 7A/DIV
I_L1, 7A/DIV
PWM2, 5V/DIV
PWM1, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (I_L1, I_L2, and I_L3)
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle after the PWM pulse of the
previous phase. The peak-to-peak current for each phase is
about 7A, and the DC components of the inductor currents
combine to feed the load.
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine the equation representing an
individual channel peak-to-peak inductor current.
I_{PP =} ⁽_---V----^I_--^N_-----^–_{-L----V-⋅---}^O_f--S---^U_--⋅--^T_--V-⁾_---I-^â‹_-N---V----^O_----^U_-----^T_-
(EQ. 1)
In Equation 1, V_IN and V_OUT are the input and output
voltages respectively, L is the single-channel inductor value,
and f_S is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
I_C(PP) =
(_{---V----I--N-----}–_-----N------⋅_{----V----O-----U----T---})_----⋅_{----V----O----U-----T-}
L
⋅
f_S
⋅
V
IN
(EQ. 2)
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has
11.9A_RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
CHANNEL 2
INPUT CURRENT
CHANNEL 1
INPUT CURRENT
1µs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND
INPUT-CAPACITOR RMS CURRENT FOR
3-PHASE CONVERTER
Active Pulse Positioning (APP) Modulated PWM
Operation
The controllers use a proprietary Active Pulse Positioning
(APP) modulation scheme to control the internal PWM
signals that command each channel’s driver to turn their
upper and lower MOSFETs on and off. The time interval in
which a PWM signal can occur is generated by an internal
clock, whose cycle time is the inverse of the switching
frequency set by the resistor connected to the FS pin. The
advantage of Intersil’s proprietary Active Pulse Positioning
(APP) modulator is that the PWM signal has the ability to
turn on at any point during this PWM time interval, and turn
off immediately after the PWM signal transitions high. This is
important because it allows the controllers to quickly
respond to output voltage drops associated with current load
spikes, while avoiding the ring back affects associated with
other modulation schemes.
The PWM output state is driven by the position of the error
amplifier output signal, V_COMP minus the current correction
signal relative to the proprietary modulator ramp waveform as
illustrated in Figure 4. At the beginning of each PWM time
interval, this modified V_COMP signal is compared to the
internal modulator waveform. As long as the modified V_COMP
voltage is lower then the modulator waveform voltage, the
PWM signal is commanded low. The internal MOSFET driver
detects the low state of the PWM signal and turns off the
18
FN6520.3
October 8, 2010